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AM3352BZCZD80 参数 Datasheet PDF下载

AM3352BZCZD80图片预览
型号: AM3352BZCZD80
PDF下载: 下载PDF文件 查看货源
内容描述: 的Sitara AM335x ARM Cortex-A8的微处理器(MPU ) [Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs)]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 236 页 / 2887 K
品牌: TI [ TEXAS INSTRUMENTS ]
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AM3359, AM3358, AM3357  
AM3356, AM3354, AM3352  
SPRS717F OCTOBER 2011REVISED APRIL 2013  
www.ti.com  
5.6.2.2.3 DDR2 CK and ADDR_CTRL Routing  
Figure 5-44 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of  
signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length  
A is the majority of the total length of signal path AB and AC.  
A1  
T
A
AM335x  
A1  
Figure 5-44. CK and ADDR_CTRL Routing and Topology  
Table 5-54. CK and ADDR_CTRL Routing Specification(1)(2)  
NO.  
1
PARAMETER  
MIN  
TYP  
MAX  
2w  
UNIT  
Center-to-center CK spacing  
2
CK differential pair skew length mismatch(2)(3)  
25  
mils  
mils  
3
CK B-to-CK C skew length mismatch  
25  
4
Center-to-center CK to other DDR2 trace spacing(4)  
CK and ADDR_CTRL nominal trace length(5)  
4w  
5
CACLM-50  
CACLM  
CACLM+50  
100  
mils  
mils  
mils  
6
ADDR_CTRL-to-CK skew length mismatch  
7
ADDR_CTRL-to-ADDR_CTRL skew length mismatch  
Center-to-center ADDR_CTRL to other DDR2 trace spacing(4)  
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(4)  
ADDR_CTRL A-to-B and ADDR_CTRL A-to-C skew length mismatch(2)  
ADDR_CTRL B-to-C skew length mismatch  
100  
8
4w  
3w  
9
10  
11  
100  
100  
mils  
mils  
(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.  
(2) Series terminator, if used, should be located closest to the AM335x device.  
(3) Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in Table 5-46.  
(4) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(5) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.  
Figure 5-45 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to  
point. Skew matching across bytes is not needed nor recommended.  
DQ[0]  
A1  
DQ[1]  
AM335x  
Figure 5-45. DQS[x] and DQ[x] Routing and Topology  
168  
Peripheral Information and Timings  
Copyright © 2011–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352  
 
 
 
 
 
 
 
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