AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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5.6.2.1.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper LPDDR interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, AM335x device LPDDR
power, and AM335x device LPDDR ground connections. Table 5-37 contains the specification for the HS
bypass capacitors as well as for the power connections on the PCB.
Table 5-37. High-Speed Bypass Capacitors
NO.
1
PARAMETER
MIN
MAX
UNIT
HS bypass capacitor package size(1)
0402 10 mils
2
Distance from HS bypass capacitor to device being bypassed
Number of connection vias for each HS bypass capacitor(2)
250
30
mils
Vias
mils
3
2
1
1
4
Trace length from bypass capacitor contact to connection via
5
Number of connection vias for each AM335x VDDS_DDR and VSS terminal
Trace length from AM335x VDDS_DDR and VSS terminal to connection via
Number of connection vias for each LPDDR device power and ground terminal
Trace length from LPDDR device power and ground terminal to connection via
AM335x VDDS_DDR HS bypass capacitor count(3)
Vias
mils
6
35
7
Vias
mils
8
35
9
10
0.6
8
Devices
μF
10 AM335x VDDS_DDR HS bypass capacitor total capacitance
11 LPDDR device HS bypass capacitor count(3)(4)
12 LPDDR device HS bypass capacitor total capacitance(4)
Devices
μF
0.4
(1) LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Per LPDDR device.
5.6.2.1.2.8 Net Classes
Table 5-38 lists the clock net classes for the LPDDR interface. Table 5-39 lists the signal net classes, and
associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the
termination and routing rules that follow.
Table 5-38. Clock Net Class Definitions
CLOCK NET CLASS AM335x PIN NAMES
CK
DDR_CK and DDR_CKn
DDR_DQS0
DQS0
DQS1
DDR_DQS1
Table 5-39. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
AM335x PIN NAMES
NET CLASS
ADDR_CTRL
CK
DDR_BA[1:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE
DQ0
DQ1
DQS0
DQS1
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
154
Peripheral Information and Timings
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