ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009
TYPICAL CHARACTERISTICS – ADS62P29/28
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,
LVDS output interface, 32K point FFT (unless otherwise noted)
SNR CONTOUR, 0 dB GAIN, UP TO 500 MHz
250
240
66
65
65.5
64
66.5
67
69
68
220
200
180
160
140
120
100
80
64.5
70
66
68
65.5
65
67
66.5
69
70
71
67
65
65.5
66
69
66.5
68
71
70
100
64.5
20
50
150
200
250
300
350
400
450
500
fIN - Input Frequency - MHz
64
65
66
67
68
69
70
71
72
SNR - dBFS
M0048-28
Figure 91.
SNR CONTOUR, 6 dB GAIN, UP TO 800 MHz
250
240
66
64.5
66.5
65.5
64
65
62
63.5
63
61
62.5
220
200
180
160
140
120
100
80
61.5
65
65.5
66
64.5
66.5
64
63
62.5
63.5
62
61.5
65
64
64.5
66.5
65.5
66
67.5
62.5
61.5
63.5
63
350
62
20
50
100
150
200
250
300
400
450
500
fIN - Input Frequency - MHz
60
61
62
63
64
65
66
67
68
SNR - dBFS
M0048-29
Figure 92.
Copyright © 2009, Texas Instruments Incorporated
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