ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS – COMMON PLOTS
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,
LVDS output interface, 32K point FFT (unless otherwise noted)
CROSSTALK vs FREQUENCY
CMRR vs FREQUENCY
−76
−80
−84
−88
−92
−96
−100
−30
−35
−40
−45
−50
−55
−60
−65
−70
Signal amplitude on aggressor channel at −0.3 dBFS
0
50
100
150
200
250
300
20
70
120
170
220
270
f − Frequency − MHz
f − Frequency − MHz
G070
G069
Figure 83.
Figure 84.
POWER DISSIPATION vs SAMPLING FREQUENCY
DRVDD CURRENT vs SAMPLING FREQUENCY
= 2.5 MHz
1.4
1.2
1.0
0.8
0.6
0.4
140
120
100
80
f
IN
= 2.5 MHz
f
IN
LVDS
LVDS
60
CMOS
CMOS, No Load
CMOS, 15 pF Load
40
20
0
25
50
75
100 125 150 175 200 225 250
− Sampling Frequency − MSPS
25
50
75
100 125 150 175 200 225 250
f − Sampling Frequency − MSPS
S
f
S
G072
G073
Figure 85.
Figure 86.
48
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