ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009
TYPICAL CHARACTERISTICS – ADS62P28 (continued)
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,
LVDS output interface, 32K point FFT (unless otherwise noted)
SNR vs AVDD SUPPLY VOLTAGE
AV = 3.3 V
PERFORMANCE vs DRVDD SUPPLY VOLTAGE
86
85
84
83
82
81
80
79
78
78
71.00
70.75
70.50
70.25
70.00
AV = 3.3 V
DD
DD
77
76
75
74
73
72
71
70
f
= 20 MHz
IN
SFDR
AV = 3.15 V
DD
AV = 3.6 V
DD
SNR
DRV = 1.8 V
DD
f
IN
= 20 MHz
1.70
1.74
1.78
1.82
1.86
1.90
−40
−20
T
0
20
40
60
80
− Free-Air Temperature − °C
DRV − Supply Voltage − V
DD
A
G064
G065
Figure 78.
Figure 79.
PERFORMANCE vs INPUT CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
96
94
92
90
88
86
84
82
80
76
90
88
86
84
82
80
78
76
76
f
IN
= 20 MHz
f
IN
= 60 MHz
75
74
73
72
71
70
69
68
75
74
73
72
71
70
69
68
SFDR
SFDR
SNR
SNR
74
0.0
0.5
1.0
1.5
2.0
2.5
30
35
40
45
50
55
60
65
Input Clock Amplitude − V
Input Clock Duty Cycle − %
PP
G066
G067
Figure 80.
Figure 81.
PERFORMANCE IN EXTERNAL REFERENCE MODE
90
88
86
84
82
80
78
f
= 60 MHz
IN
External Reference Mode
SFDR
76
74
72
70
68
SNR
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V
VCM
− VCM Voltage − V
G068
Figure 82.
Copyright © 2009, Texas Instruments Incorporated
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