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ADS62P49IRGCT 参数 Datasheet PDF下载

ADS62P49IRGCT图片预览
型号: ADS62P49IRGCT
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道14位/ 12位, 250 / 210 - MSPS ADC,具有DDR LVDS和并行CMOS输出 [Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs]
分类和应用: 双倍数据速率
文件页数/大小: 76 页 / 2133 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635AAPRIL 2009REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
SERIAL REGISTER MAP  
(1)  
Table 7. Summary of Functions Supported by Serial Interface  
REGISTER  
REGISTER FUNCTIONS  
ADDRESS  
A7–A0  
IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
0
D0  
00  
<RESET>  
0
0
0
0
0
<SERIAL  
Software Reset  
READOUT>  
20  
0
0
0
0
0
<ENABLE  
LOW  
0
0
SPEED  
MODE>  
3F  
0
0
<REF>  
0
0
0
0
0
0
<STANDBY>  
0
0
Internal or external reference  
40  
41  
0
0
0
0
0
0
<POWER DOWN MODES>  
<LVDS CMOS>  
Output interface  
0
0
44  
50  
<CLKOUT EDGE CONTROL>  
0
0
0
0
<ENABLE INDIVIDUAL  
CHANNEL CONTROL>  
0
0
<DATA FORMAT>  
2s comp or offset binary  
51  
52  
53  
<CUSTOM PATTERN LOW>  
0
0
0
<CUSTOM PATTERN HIGH>  
<ENABLE OFFSET  
0
CORRECTION – CH A>  
55  
57  
<GAIN PROGRAMMABILITY – CH A>  
<OFFSET CORRECTION TIME  
CONSTANT – CH A>  
0 to 6 dB in 0.5 dB steps  
0
<FINE GAIN ADJUST – CH A>  
+0.001 dB to +0.134 dB, in 128 steps  
62  
63  
66  
0
0
0
0
0
0
0
0
<TEST PATTERNS – CH A>  
<OFFSET PEDESTAL – CH A>  
<ENABLE OFFSET  
0
0
0
0
0
0
CORRECTION – CH B>  
68  
6A  
<GAIN PROGRAMMABILITY – CH B>  
<OFFSET CORRECTION TIME  
CONSTANT – CH B>  
0 to 6 dB in 0.5 dB steps  
0
<FINE GAIN ADJUST – CH B>  
+0.001 dB to +0.134 dB, in 128 steps  
75  
76  
0
0
0
0
0
0
0
<TEST PATTERNS – CH B>  
<OFFSET PEDESTAL – CH B>  
(1) Multiple functions in a register can be programmed in a single write operation.  
20  
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Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
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