ADS131M04-Q1
ZHCSOL7A –MARCH 2022 –REVISED AUGUST 2022
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the use of the external clock input. Do not toggle CLKIN when in current-detect mode to minimize device power
consumption.
Current-detect mode is configured in the CFG, THRSHLD_MSB, and THRSHLD_LSB registers. Enable and
disable current-detect mode by toggling the CD_EN bit in the CFG register. The THRSHLD_MSB and
THRSHLD_LSB registers contain the CD_THRSH[23:0] bits that represent the digital comparator threshold
value during current detection.
The number of samples used for current detection are programmed by the CD_LEN[2:0] bits in the CFG register.
The number of samples used for current detection range from 128 to 3584.
The programmable values in CD_NUM[2:0] configure the number of samples that must exceed the threshold for
a detection to occur. The purpose of requiring multiple samples for detection is to control noisy values that may
exceed the threshold, but do not represent a high enough power level to warrant action by the host. In summary,
the conversion result must exceed the value programmed in CD_THRSH[23:0] a number of times as
represented by the value stored in CD_NUM[2:0].
The device can be configured to notify the host based on any of the results from individual channels, all
channels, or any combination of channels. The CD_ALLCH bit in the CFG register determines how many
channels are required to exceed the programmed thresholds to trigger a current detection. When the bit is 1, all
enabled channels are required to meet the current detection requirements in order for the host to be notified. If
the bit is 0, any enabled channel triggers a current detection notification if the requirements are met. Enable and
disable channels using the CHn_EN bits in the CLK register to control which combination of channels must meet
the requirements to trigger a current-detection notification.
图8-17 illustrates a flow chart depicting the current-detection process on the ADS131M04-Q1.
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