ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
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8.6.7 GLOBAL_CHOP_CFG Register (Address = 06h) [reset = 0600h]
The GLOBAL_CHOP_CFG register is shown in 图8-32 and described in 表8-19.
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图8-32. GLOBAL_CHOP_CFG Register
15
14
13
12
11
10
9
1
8
RESERVED
R/W-000b
GC_DLY[3:0]
R/W-0011b
GC_EN
R/W-0b
7
6
5
4
3
2
0
RESERVED
R/W-00000000b
表8-19. GLOBAL_CHOP_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
RESERVED
R/W
000b
Reserved
Always write 000b
12:9
GC_DLY[3:0]
R/W
0011b
Global chop delay selection
Delay in modulator clock periods (tMOD) before measurement begins.
0000b = 2
0001b = 4
0010b = 8
0011b = 16
0100b = 32
0101b = 64
0110b = 128
0111b = 256
1000b = 512
1001b = 1024
1010b = 2048
1011b = 4096
1100b = 8192
1101b = 16484
1110b = 32768
1111b = 65536
8
GC_EN
R/W
R/W
0b
Global chop enable
0b = Disabled
1b = Enabled
7:0
RESERVED
00000000b Reserved
Always write 00000000b
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