ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
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8.6.13 CH0_GCAL_MSB Register (Address = 0Ch) [reset = 8000h]
The CH0_GCAL_MSB register is shown in 图8-38 and described in 表8-25.
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图8-38. CH0_GCAL_MSB Register
15
14
13
12
11
10
9
1
8
0
GCAL0_MSB[15:8]
R/W-10000000b
7
6
5
4
3
2
GCAL0_MSB[7:0]
R/W-00000000b
表8-25. CH0_GCAL_MSB Register Field Descriptions
Bit
15:0
Field
GCAL0_MSB[15:0]
Type
Reset
Description
Channel 0 gain calibration register bits [23:8]
Unsigned number for the gain range from 0.0 to 2.0 x (224 –1) / 224
R/W
10000000
00000000b
8.6.14 CH0_GCAL_LSB Register (Address = 0Dh) [reset = 0000h]
The CH0_GCAL_LSB register is shown in 图8-39 and described in 表8-26.
Return to the Summary Table.
图8-39. CH0_GCAL_LSB Register
15
14
13
12
11
10
2
9
1
8
0
GCAL0_LSB[7:0]
R/W-00000000b
7
6
5
4
3
RESERVED
R-00000000b
表8-26. CH0_GCAL_LSB Register Field Descriptions
Bit
Field
Type
Reset
00000000b Channel 0 gain calibration register bits [7:0]
Unsigned number for the gain range from 0.0 to 2.0 x (224 –1) / 224
00000000b Reserved
Always reads 00000000b
Description
15:8
GCAL0_LSB[7:0]
R/W
7:0
RESERVED
R
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