ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
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8.6.11 CH0_OCAL_MSB Register (Address = 0Ah) [reset = 0000h]
The CH0_OCAL_MSB register is shown in 图8-36 and described in 表8-23.
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图8-36. CH0_OCAL_MSB Register
15
14
13
12
11
10
9
1
8
0
OCAL0_MSB[15:8]
R/W-00000000b
7
6
5
4
3
2
OCAL0_MSB[7:0]
R/W-00000000b
表8-23. CH0_OCAL_MSB Register Field Descriptions
Bit
15:0
Field
OCAL0_MSB[15:0]
Type
Reset
Description
R/W
00000000
Channel 0 offset calibration register bits [23:8]
00000000b Value provided in two's complement format
8.6.12 CH0_OCAL_LSB Register (Address = 0Bh) [reset = 0000h]
The CH0_OCAL_LSB register is shown in 图8-37 and described in 表8-24.
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图8-37. CH0_OCAL_LSB Register
15
14
13
12
11
10
2
9
1
8
0
OCAL0_LSB[7:0]
R/W-00000000b
7
6
5
4
3
RESERVED
R-00000000b
表8-24. CH0_OCAL_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
15:8
OCAL0_LSB[7:0]
R/W
00000000b Channel 0 offset calibration register bits [7:0]
Value provided in two's complement format
7:0
RESERVED
R
00000000b Reserved
Always reads 00000000b
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