ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
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8.4 Device Functional Modes
图 8-10 shows a state diagram depicting the major functional modes of the ADS131B04-Q1 and the transitions
between these modes.
POR, pin reset, or
RESET command
Reset
complete
Reset
STANDBY
Standby
Mode
Continuous
Conversion Mode
WAKEUP && GC_EN
STANDBY
GC_EN
WAKEUP
&& GC_EN
GC_EN
Global Chop
Mode
图8-10. State Diagram Depicting Device Functional Modes
8.4.1 Power-Up and Reset
The ADS131B04-Q1 is reset in one of three ways: by a power-on reset (POR), by the SYNC/RESET pin, or by a
RESET command. After a reset occurs, the configuration registers are reset to the default values and the device
begins generating conversion data as soon as a valid MCLK is provided. In all three cases a low to high
transition on the DRDY pin indicates that the SPI interface is ready for communication. The device ignores any
SPI communication before this point.
8.4.1.1 Power-On Reset
Power-on reset (POR) is the reset that occurs when a valid supply voltage is first applied. The POR process
requires tPOR to complete from when the supply voltages reach 90% of their nominal value to allow for the
internal circuitry to power up. The DRDY pin transitions from low to high immediately after tPOR indicating the SPI
interface is ready for communication.
8.4.1.2 SYNC/RESET Pin
The SYNC/RESET pin is an active low, dual-function pin that generates a reset if the pin is held low for longer
than tw(RSL). The device maintains a reset state until SYNC/RESET is returned high. The host must wait for at
least tREGACQ after SYNC/RESET is brought high or for the DRDY rising edge before communicating with the
device.
8.4.1.3 RESET Command
The ADS131B04-Q1 can be reset via the SPI RESET command. The device communicates in frames of a fixed
length. Six words are required to complete a frame on the ADS131B04-Q1. The RESET command is transmitted
in the first word of the data frame on DIN, but the command is not latched and executed by the device until the
entire frame is complete. Terminating the frame early causes the RESET command to be ignored. A device reset
occurs immediately after the RESET command is latched. The host must wait for at least tREGACQ or for the
DRDY rising edge before communicating with the device.
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