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78Q8430-100IGT/F 参数 Datasheet PDF下载

78Q8430-100IGT/F图片预览
型号: 78Q8430-100IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100以太网MAC和PHY [10/100 Ethernet MAC and PHY]
分类和应用: 电信集成电路编码器以太网局域网(LAN)标准
文件页数/大小: 88 页 / 1209 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78Q8430 Data Sheet  
DS_8430_001  
7.5 QUE Registers  
7.5.1 Packet Control Word Register  
Name: PCWR  
Reset Val: 0x0000_0000  
Block: QUE  
Address: 0x000  
Bits  
Type Default Description  
31:30  
29:25  
X
Reserved  
WO  
N/A  
Preload  
The number of bytes to pre-load into the MAC TX FIFO before the  
frame begins transmission to the PHY. This may need to be non-zero  
for large IP headers that want to have the checksum inserted to ensure  
the checksum is not transmitted before the end of the header is loaded.  
24:16  
15:10  
WO  
WO  
N/A  
N/A  
Packet ID  
The 9-bit ID value used to identify this packet in the TX status FIFO.  
IP Header Offset  
Offset in bytes to the IP header in this frame. If this value is non-zero  
then the IP header checksum will be corrected.  
9
8
WO  
WO  
N/A  
N/A  
Append CRC  
When set, the transmitter shall append the correct CRC checksum to  
the end of the frame.  
Fix CRC  
When set, the transmitter shall correct the existing CRC checksum on  
the end of the packet.  
7
6
X
Reserved  
WO  
N/A  
N/A  
N/A  
Disable Padding  
For small packets (<64 Bytes).  
5
4
WO  
WO  
Late Notify  
Interrupt on completion.  
Early Notify  
Interrupt at beginning of transmission.  
Interrupt on excessive collisions.  
Disable deferral timeout.  
Enable fast back-off timer.  
Reserved  
3
2
1
0
WO  
WO  
WO  
X
N/A  
N/A  
N/A  
7.5.2 Packet Size Register  
Name: PSZR Reset Val: 0x0000_0000  
Block: QUE  
Address: 0x004  
Bits  
Type  
Default Description  
31:16  
15:0  
X
Reserved  
RW  
0000  
Packet Size  
The size, in bytes, of the packet that will be added to the QUE.  
56  
Rev. 1.2