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78Q8430-100IGT/F 参数 Datasheet PDF下载

78Q8430-100IGT/F图片预览
型号: 78Q8430-100IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100以太网MAC和PHY [10/100 Ethernet MAC and PHY]
分类和应用: 电信集成电路编码器以太网局域网(LAN)标准
文件页数/大小: 88 页 / 1209 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_8430_001  
78Q8430 Data Sheet  
7.5.3 Setup Transmit Data Register  
Name: STDR  
Reset Val: 0x0000_0000  
Block: QUE  
Address: 0x008  
Bits  
31:25  
24  
Type Default Description  
X
Reserved  
RW  
Endian  
The network transmit byte order.  
Set = big endian (Most significant byte transmit first)  
Clear = little endian (Least significant byte transmit first)  
23:20  
19:18  
X
Reserved  
RW  
00  
00  
Start Offset  
The number of bytes to ignore on the first data word written for this  
buffer. This byte mask is applied any time the Count value is  
non-zero. After each time it is applied, however, it is reset to zero such  
that it is really only applied on the first write.  
17:16  
RW  
End Offset  
The number of bytes to ignore on the last data word written for this  
buffer. This byte mask is applied any time the Count value is zero.  
Unlike the Start Offset, the End Offset is not self clearing. This means  
that the End Offset will be applied to all writes to the QUE once the  
Count value reaches zero, unless the host clears the End Offset. The  
remainder of PSZR will override the End Offset when a write occurs  
and the PSZR value is less than four.  
15:14  
13:0  
X
Reserved  
RW  
0000  
Count  
The total number of writes needed to complete the buffer minus one.  
This counter decrements on each write operation to the QUE. This  
counter decrements on each write operation to the QUE until it reaches  
zero. The Count value will remain zero until the next host write. The  
value written here must be one less than the number of writes in the  
buffer so that the Count value will equal zero on the last write and  
cause the End Offset to be applied.  
Note: The PCWR and PSZR must be set before writing to the STDR.  
7.5.4 Transmit Data Register  
Name: TDR  
Reset Val: 0x0000_0000  
Block: QUE  
Address: 0x00C  
Bits  
Type Default Description  
31:0  
WO  
N/A  
Packet Data to Add to the QUE  
Data written to this register is added to the QUE to which the register  
belongs.  
7.5.5 Receive Data Register  
Name: RDR  
Reset Val: 0x0000_0000  
Type Default Description  
RO N/A  
Packet Data Read from the QUE  
Block: QUE  
Address: 0x010  
Bits  
1:0  
Data read from this register is shifted out of the QUE to which the  
register belongs. The RPSR should be consulted to make sure data is  
available before reading this register.  
Rev. 1.2  
57