78Q8430 Data Sheet
DS_8430_001
7.3 CTL Register Overview
Page
59
Address Symbol
Name
0x100
0x104
0x108
0x10C
0x110
0x114
0x118
0x11C
0x120
0x124
0x128
0x12C
0x130
0x134
0x138
0x13C
0x140
0x144
0x148
0x14C
0x150
0x154
0x158
0x15C
0x160
0x164
0x168
0x16C
0x170
DMA
DMA Slave Mode Control and Status
Receive Packet Status FIFO
Transmit Packet Status FIFO
Transmit Producer Status
Receive Producer Status
RPSR
59
TPSR
59
TPROS
RPROS
Reserved
GBI_ID
GBI_CS
Reserved
Reserved
RTTR
60
60
61
61
Part ID Register
Configuration Register
61
61
61
62
62
63
63
63
63
64
Receive to Transmit Transfer Register
Frame Disposition Register
FDR
RFBSR
RDSR
Receive FIRST BLOCK Status Register
Receive Data Status Register
BIST Control Register
BCR
BBDR
BIST Bypass Mode Data Register
Station Management Data Register
Station Management Control and Address Register
PROM Data
MDDAR
MDCAR
PRDR
PRCR
PROM Control
Reserved
MCR
64
MAC Control Register
Reserved
Reserved
Reserved
CDR
65
65
66
66
Count Data Register
CCR
Count Control Register
Count Management Register
Snoop Control Register
CMR
SNCR
0x174 -
0x17C
Reserved
0x180
0x184
0x188
0x18C
0x190
0x194
0x198
0x19C
0x1A0
0x1A4
0x1A8
0x1AC
IDCR
66
66
67
67
67
Interrupt Delay Count Register
Pause Delay Count Register
Host Not Responding Count Register
Wake Up Status Register
PDCR
HNRCR
WUSR
WMVR
Reserved
PMCAP
PMCSR
CAR
Water Mark Values Register
67
68
68
69
69
Power Management Capabilities
Power Management Control and Status
Address of CAM rule being accessed
Rule Match Register
RMR
RCR
Rule Control Register
Reserved
54
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
