78Q8430 Data Sheet
DS_8430_001
6.12.5 10Base-T Receive
The 78Q8430 PHY receives Manchester encoded 10BASE-T data through the twisted pair inputs and
re-establishes logic levels through a slicer with a smart squelch function. The slicer automatically adjusts
its level after valid data with the appropriate levels are detected. Data is passed on to the CDR where the
clock is recovered and data is re-timed and passed through a Manchester decoder. From here, data
enter the serial to parallel converter for transmission to the MAC via the media independent interface.
Interface to the twisted pair media is through a 1:1 transformer. Polarity information is detected and
corrected in internal circuitry.
6.12.6 SQE Test
The 78Q8430 PHY supports the signal quality error (SQE) function detailed in IEEE-802.3. At an interval
of 1µs after each negative transition of the TXEN pin in 10BASE-T mode, the COL pin will go high for a
period of 1µs. SQE is not signaled if a collision is detected during transmission. This function can be
disabled through register bit MR16.11.
6.12.7 Polarity Correction
The 78Q8430 PHY is capable of either automatic or manual polarity reversal for 10BASE-T and
auto-negotiation. These features are controlled by the PHY management register MR16, bits APOL and
RVSPOL. The default is automatic mode, where APOL is negated and RVSPOL indicates if the detection
circuitry has inverted the input signal. To enter manual mode, APOL needs to be asserted and then
RVSPOL will control the signal polarity.
6.12.8 Natural Loopback
The natural loop back function can be enabled by setting register bit MR16.10. With natural loop back
enabled, whenever the 78Q8430 PHY is transmitting and not receiving on the twisted pair media
(10BASE-T Half Duplex mode), data on the TXD pins is looped back onto the RXD pins. During a
collision, data from the RXI pins is routed to the RXD pins.
50
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
