78Q8430 Data Sheet
DS_8430_001
7 Register Descriptions
7.1 Register Overview
The 78Q8430 has 10 address bits for a total address space of 1024 bytes. This address space is divided
into four 256-location blocks: QUE, CTL, Reserved and SNOOP.
The QUE section contains registers used to control transmit and receive queues. Each queue is
allocated eight 32-bit registers for a maximum of eight queues supported.
The CTL section contains control registers used to control the behavior of 78Q8430.
A block of 256 addresses is reserved for future use.
The SNOOP section is mapped to cache memory via the Snoop Control Register.
Address Range
Group
QUE
0x000
…
0x0FF
0x100
…
CTL
0x1FF
0x200
…
Reserved
SNOOP
0x2FF
0x300
…
0x3FF
52
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
