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78Q8430-100IGT/F 参数 Datasheet PDF下载

78Q8430-100IGT/F图片预览
型号: 78Q8430-100IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100以太网MAC和PHY [10/100 Ethernet MAC and PHY]
分类和应用: 电信集成电路编码器以太网局域网(LAN)标准
文件页数/大小: 88 页 / 1209 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_8430_001  
78Q8430 Data Sheet  
6.12.9 Auto-Negotiation  
The 78Q8430 PHY supports the auto-negotiation functions of Clause 28 of IEEE-802.3. This function can  
be controlled via register settings. The auto-negotiation function defaults to on and bit MR0[12],  
ANEGEN, is high after reset. Software can disable the auto-negotiation function by writing to bit MR0[12].  
The contents of register MR4 are sent to the PHY’s link partner during auto-negotiation, coded in fast link  
pulses. Bits MR4.8:5 reflect the state of the TECH[2:0] bits after reset. If TECH[2:0] = 111b, then all 4  
bits are high. If TECH[2:0] = 001b, then only bit 5 is high. After reset, software can change any of these  
bits from a 1 to a 0.  
With auto-negotiation enabled, the 78Q8430 PHY will start sending fast link pulses at power on, loss of  
link or a command to restart. At the same time, it will look for either 10BASE-T idle, 100BASE-TX idle or  
fast link pulses from its link partner. If either idle pattern is detected, the 78Q8430 PHY configures itself  
in half- duplex mode at the appropriate speed. If it detects fast link pulses, it decodes and analyzes the  
link code transmitted by the link partner. When three identical link code words are received (ignoring the  
acknowledge bit), the link code word is stored in register 5. Upon receiving three more identical link code  
words, with the acknowledge bit set, the 78Q8430 PHY configures itself to the highest priority technology  
common to the two link partners. The technology priorities are, in descending order:  
100BASE-TX, Full Duplex.  
100BASE-TX, Half Duplex.  
10BASE-T, Full Duplex.  
10BASE-T, Half Duplex.  
Once auto-negotiation is complete, register bits MR18[11:10] will reflect the actual speed and duplex that  
was chosen. If auto-negotiation fails to establish a link for any reason, register bit MR18[12] will reflect  
this and auto negotiation will restart from the beginning. Writing a one to bit MR0[9], RANEG, will also  
cause auto negotiation to restart.  
6.12.10 LED Indicators  
Two LED pins can be used to indicate various states of operation of the 78Q8430 PHY. The default  
configuration uses LED0 to indicate the link is up and LED1 to indicate either RX or TX activity. LED0  
and LED1 may be redefined via MR23. There is no direct hardware for controlling the MAC from the PHY  
LED status, therefore software drivers must obtain the DUPLEX and SPEED parameters from the PHY  
register MR18[11:10] and configure the MAC accordingly.  
6.12.11 PHY Interrupts  
The 78Q8430 PHY has an Interrupt signal that is asserted whenever any of the eight interrupt bits of  
MR17[7:0] are set. The PHY bit in the Host Interrupt Register (HIR) is set to indicate and interrupt from  
the PHY. Individual PHY interrupt conditions can be enabled via MR17, bits 15:8, the PHY Interrupt  
Enable bits. PHY interrupt bits are cleared when MR17 is read.  
6.12.12 Internal Clock PLL  
When the internal clock mode is selected by the CLKMODE pin, the 100 MHz system clock is provided by  
a PLL inside the PHY. This PLL multiplies the frequency of the 25 MHz PLL crystal oscillator up to the  
100 MHz needed to run the system clock.  
When the PHY is powered down, the PLL used to generate the internal system clock is also powered  
down and ceases to function. For this reason, the internal PHY should never be powered down when the  
internal system clock is selected by the CLKMODE pin.  
There is no external visibility for the system clock when the internal clock mode is selected. The GBI  
interface must therefore always be used in asynchronous bus mode when the internal clock mode is  
used.  
Rev. 1.2  
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