Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Table 48: EECTRL Bits for the 3-Wire Interface
Read/
Write
Control
Bit
Name
Description
7
WFR
W
Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed
until a rising edge is seen on the data line. This bit can be used during
the last byte of a Write command to cause the INT5 interrupt to occur
when the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ = 0.
6
5
BUSY
HiZ
R
Asserted while the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
W
Indicates that the SD signal is to be floated to high impedance immediately
after the last SCK rising edge.
4
RD
W
W
Indicates that EEDATA is to be filled with data from EEPROM.
3:0
CNT[3:0]
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data will be read MSB first and right
justified into the low order bits of EEDATA. If RD=0, CNT bits will be sent
MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA will simply obey the HiZ bit.
The timing diagrams in Figure 11 through Figure 15 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 11 through Figure 15
are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM
will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should
then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to
a low-Z state.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- No HiZ
SCLK (output)
D7
D6
D5
D4
D3
D2
SDATA (output)
SDATA output Z
BUSY (bit)
(LoZ)
Figure 11: 3-Wire Interface. Write Command, HiZ=0
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ
SCLK (output)
D7
D6
D5
D4
D3
D2
SDATA (output)
SDATA output Z
BUSY (bit)
(LoZ)
(HiZ)
Figure 12: 3-Wire Interface. Write Command, HiZ=1
© 2005-2010 TERIDIAN Semiconductor Corporation
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