Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Table 49: SPI Command Description
Description
Command
11xx xxxx ADDR Byte0 ... ByteN Read data starting at ADDR. The ADDR will auto-increment until PCSZ
is raised. Upon completion:
SP__CMD=11xx xxxx, SP_ADDR=ADDR+N+1.
No MPU interrupt is generated if the command is 1100 0000. Otherwise,
an SPI interrupt is generated.
10xx xxxx ADDR Byte0 ... ByteN Write data starting at ADDR. The ADDR will auto-increment until PCSZ
is raised. Upon completion:
SP_CMD=10xx xxxx, SP_ADDR=ADDR+N+1.
No MPU interrupt is generated if the command is 1000 0000. Otherwise,
an SPI interrupt is generated.
Certain I/O RAM registers can be written and read using the SPI port (see Table 50). However, the MPU
takes priority over the I/O RAM bus, and SPI operation may fail without notice. To avoid this situation, the
SPI host should send a command other than 11xxxxxx or 10xxxxxx (read or write) before the actual read
or write command. The SPI slave interface will load the command register and generate an INT2 inter-
rupt upon receiving the command. The MPU should service the interrupt and halt any external data memory
operations to effectively grant the bus to the SPI. When the SPI host finishes, it should send another
command so the MPU can release the bus. There are no issues with Data RAM access; SPI and the
MPU will share the bus with no conflicts for Data RAM access.
Table 50: I/O RAM Registers Accessible via SPI
Name
Address (hex) Bit Range
Read/Write
RW
RW
RW
RW
RW
R
CE0
CE1
CE2
2000
2001
7:3
7:0
2002
2004
2005
2006
5:3, 1:0
7:6, 3:0
5:2, 0
7:0
CONFIG0
CONFIG1
VERSION
CONFIG2
DIO0
2007
7:0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
2008
7:6, 4:0
6:4, 2:0
7:6, 3:2
1:0
DIO1 to DIO6
−
2009 to 200E
200F
2060
RTM0H
RTM0L
RTM1H
RTM1L
RTM2H
RTM2L
RTM3H
RTM3L
PLS_W
PLS_I
2061
7:0
2062
1:0
2063
7:0
2064
1:0
2065
7:0
2066
1:0
2067
7:0
2080
7:0
2081
7:0
SLOT0 to SLOT9 2090 to 209A
7:0
CE3
CE4
CE5
209D
20A7
20A8
20A9
20AC
20AD
20AF
3:0
7:0
7:0
7:5, 3:0
5:4, 1:0
5:4, 1:0
2:0
WAKE
CONFIG3
CONFIG4
−
RW
RW
RW
50
© 2005-2010 TERIDIAN Semiconductor Corporation
v1.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
