Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Section 4.1 I/O RAM and SFR Map – Functional Order. The LCD drivers are supported by the four common
pins (COM0 – COM3).
1.5.11 LCD Drivers – 71M6532D/F
The 71M6532D/F contains a total of 67 dedicated and multiplexed LCD drivers, which are grouped as
follows:
• 15 dedicated LCD segment drivers (SEG0 to SEG2, SEG8, SEG12 - SEG18, SEG20 – SEG23)
• 4 drivers multiplexed with the SPI port (SEG3 to SEG6)
• 2 drivers multiplexed with MUX_SYNC (SEG7) or CKTEST (SEG19)
• 3 drivers multiplexed with the ICE interface (SEG9 to SEG11)
• 43 multi-use LCD/DIO pins described in Section 1.5.8 Digital I/O – 71M6532D/F.
With a minimum of 15 driver pins always available and a total of 67 driver pins in the maximum configuration,
the device is capable of driving between 60 to 268 pixels of an LCD display with 25% duty cycle. At eight
pixels per digit, this corresponds to 7.5 to 33.5 digits.
For each multi-use pin, the corresponding LCD_BITMAP[ ] bit (see Section 1.5.8 Digital I/O – 71M6532D/F),
is used to select the pin for DIO or LCD operation. The mapping of the LCD_BITMAP[ ] bits is specified in
Section 4.1 I/O RAM and SFR Map – Functional Order. The LCD drivers are supported by the four common
pins (COM0 – COM3).
1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
The LCD interface is flexible and can drive 7-segment digits, 14-segment digits or enunciator symbols.
The LCD bias may be compensated for temperature using the LCD_DAC[2:0] bits in I/O RAM. The bias
may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in mission mode and brownout modes,
VBAT in LCD mode). When the LCD_DAC[2:0] bits are set to 000, the DAC is bypassed and powered
down. This can be used to reduce current in LCD mode.
Segment drivers SEG18 and SEG19 can be configured to blink at either 0.5 Hz or 1 Hz. The blink rate is
controlled by LCD_Y. There can be up to four pixels/segments connected to each of these drivers.
LCD_BLKMAP18[3:0] and LCD_BLKMAP19[3:0] identify which pixels, if any, are to blink. The most
significant bit corresponds to COM3, the least significant to COM0.
1.5.13 Battery Monitor
The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure
Enable) bit is set. While BME is set, an on-chip 45 kΩ load resistor is applied to the battery and a scaled
fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of
the ADC conversion is available at RAM address 0x0B. BME is ignored and assumed zero when system
power is not available.
If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain
VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.
Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.
Battery measurement is not very linear but is very reproducible if properly calibrated. The best way to
perform the calibration is to set the battery input to the desired failure voltage and then have the MPU
firmware record that measurement. After this, the battery measurement logic may use the recorded value
as the battery failure limit. The same value can also be a calibration offset for any battery voltage display.
See Section 5.4.4 Battery Monitor for details regarding the ADC LSB size and the conversion accuracy.
1.5.14 EEPROM Interface
The 71M6531D/F and 71M6532D/F provide hardware support for either a two-pin or a three-wire (µ-wire)
type of EEPROM interface. The interfaces use the EECTRL and EEDATA registers for communication.
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