FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Additionally, if DIO6 and DIO7 are configured as DIO and defined as outputs, they can be used as
dedicated pulse outputs (WPULSE = DIO6, VARPULSE = DIO7) using the DIO_PW and DIO_PV bits. In
this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the
EEPROM Interface.
The PB pin is a dedicated digital input. In addition, if the optical UART is not used, OPT_TX and OPT_RX
can be configured as dedicated DIO pins, DIO1 and DIO2, respectively (see Section 1.5.6 Optical Interface).
The internal control resources selectable for the DIO pins are listed in Table 46. If more than one input is
connected to the same resource, the resources are combined using a logical OR.
Tracking DIO pins configured as outputs is useful for pulse counting without external hardware.
Either the interrupts or the counter/timer clocks can be used to count pulses on the pulse outputs
or interrupts on the CE’s power failure output.
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in
Figure 10, right), not source it from V3P3D (as shown in Figure 10, left). This is due to the resis-
tance of the internal switch that connects V3P3D to either V3P3SYS or VBAT.
Sourcing current into or out of DIO pins other than the PB pin, for example with pull-up or pull-
down resistors, should be avoided. Violating this rule will lead to increased quiescent current in
sleep and LCD modes.
MISSION
MISSION
V3P3SYS
VBAT
V3P3SYS
VBAT
LCD/SLEEP
BROWNOUT
LCD/SLEEP
BROWNOUT
V3P3D
V3P3D
HIGH
HIGH-Z
LOW
HIGH
HIGH-Z
LOW
DIO
DIO
GNDD
GNDD
Figure 10: Connecting an External Load to DIO Pins
1.5.10 LCD Drivers – 71M6531D/F
The 71M6531 contains a total of 39 dedicated and multiplexed LCD drivers which are grouped as follows:
• 11 dedicated LCD segment drivers – always available
• 3 drivers multiplexed with the ICE interface (E_TCLK, E_RST, E_RXTX) – available in normal operation
mode (when not emulating)
• 2 driver multiplexed with auxiliary signals MUX_SYNC and CKTEST (SEG7, SEG19) – available
when not used for test
• 4 drivers multiplexed with the SPI port (PCLK, PSDO, PCSZ, PSDI)
• 19 multi-use pins described in Section 1.5.7 Digital I/O – 71M6531D/F.
• 4 common drivers for multiplexing (25%, 33%, 50%, or 100% duty cycle) – always available
With a minimum of 16 driver pins always available and a total of 39 driver pins in the maximum configuration,
the device is capable of driving between 64 to 156 pixels of LCD display with 25% duty cycle. At eight pixels
per digit, this corresponds to 8 to 19 digits. At 33% duty cycle, 48 to 117 pixels can be driven.
For each multi-use pin, the corresponding LCD_BITMAP[] bit (see Section 1.5.7 Digital I/O – 71M6531D/F),
is used to select the pin for DIO or LCD operation. The mapping of the LCD_BITMAP[] bits is specified in
v1.3
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