TSC80251G2D
Table 24. Summary of Logical Instructions (2/2)
Shift Left Logical
Shift Right Arithmetic
Shift Right Logical
Swap
SLL <dest>
SRA <dest>
SRL <dest>
SWAP A
<dest> ← 0
0
<dest>
← <dest> , n= 0..msb-1
n+1
n
(CY) ← <dest>
msb
<dest>
← <dest>
msb
msb
<dest> ← <dest> , n= msb..1
n-1
n
(CY) ← <dest>
0
<dest>
← 0
msb
<dest> ← <dest> , n= msb..1
n-1
n
(CY) ← <dest>
0
A
A
7:4
3:0
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
Rm
WRj
Rm
WRj
Rm
WRj
A
Shift byte register left through the MSB
Shift word register left through the MSB
Shift byte register right
3
3
3
3
3
3
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
2
SLL
SRA
SRL
Shift word register right
Shift byte register left
Shift word register left
SWAP
Swap nibbles within ACC
Note:
1. A shaded cell denotes an instruction in the C51 Architecture.
Table 25. Summary of Multiply, Divide and Decimal-adjust Instructions
Multiply
Divide
Divide
MUL AB
MUL <dest>, <src>
DIV AB
(B:A) ← (A)×(B)
extended dest opnd ← dest opnd × src opnd
(A) ← Quotient ((A) ⁄ (B))
(B) ← Remainder ((A) ⁄ (B))
ext. dest opnd high ← Quotient (dest opnd ⁄ src opnd)
ext. dest opnd low ← Remainder (dest opnd ⁄ src opnd)
DIV <dest>, <src>
DA A
Decimal-adjust ACC
for Addition (BCD)
IF [[(A) > 9] [(AC)= 1]]
3:0
THEN (A) ← (A) + 6 !affects CY;
3:0
3:0
IF [[(A) > 9] [(CY)= 1]]
7:4
THEN (A) ← (A) + 6
7:4
7:4
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
AB
Multiply A and B
1
3
3
1
3
3
1
5
6
1
2
2
1
2
2
1
5
5
MUL
Rmd, Rms
WRjd, WRjs
AB
Multiply byte register and byte register
Multiply word register and word register
Divide A and B
12
10
11
21
1
11
10
10
20
1
DIV
Rmd, Rms
WRjd, WRjs
A
Divide byte register and byte register
Divide word register and word register
Decimal adjust ACC
DA
Note:
1. A shaded cell denotes an instruction in the C51 Architecture.
21
Rev. A - May 7, 1999
TEMIC [ TEMIC SEMICONDUCTORS ]
