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TSC80251G2D-24CB 参数 Datasheet PDF下载

TSC80251G2D-24CB图片预览
型号: TSC80251G2D-24CB
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器,串行通信接口 [8/16-bit Microcontroller with Serial Communication Interfaces]
分类和应用: 微控制器外围集成电路异步传输模式ATM通信时钟
文件页数/大小: 63 页 / 813 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
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TSC80251G2D  
Table 30. Summary of Exchange, Push and Pop Instructions  
Exchange bytes  
Exchange Digit  
Push  
XCH A, <src>  
XCHD A, <src>  
PUSH <src>  
(A) src opnd  
(A) src opnd  
(SP) (SP) +1; ((SP)) src opnd;  
(SP) (SP) + size (src opnd) - 1  
(SP) (SP) - size (dest opnd) + 1;  
dest opnd ((SP)); (SP) (SP) -1  
3:0  
3:0  
Pop  
POP <dest>  
Binary Mode  
Source Mode  
Mnemonic  
<dest>, <src>(1)  
Comments  
Bytes States Bytes States  
A, Rn  
A, dir8  
A, @Ri  
A, @Ri  
dir8  
ACC and register  
1
2
1
1
2
4
5
3
3
3
2
3
3
3
3
2
2
2
2
2
3
4
2
2
2
2
2
2
2
4
(3)  
(3)  
XCH  
ACC and direct address (on-chip RAM or SFR)  
ACC and indirect address  
3
3
4
5
XCHD  
ACC low nibble and indirect address (256 bytes)  
Push direct address onto stack  
4
5
(2)  
(2)  
2
2
#data  
#data16  
Rm  
Push immediate data onto stack  
4
5
4
5
3
5
3
4
Push 16-bit immediate data onto stack  
Push byte register onto stack  
PUSH  
WRj  
Push word register onto stack  
DRk  
Push double word register onto stack  
Pop direct address (on-chip RAM or SFR) from stack  
Pop byte register from stack  
9
8
(2)  
(2)  
dir8  
3
3
Rm  
3
5
9
2
4
8
POP  
WRj  
Pop word register from stack  
DRk  
Pop double word register from stack  
Notes:  
1. A shaded cell denotes an instruction in the C51 Architecture.  
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.  
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.  
Table 31. Summary of Conditional Jump Instructions (1/2)  
Jump conditional on status  
Jcc rel  
(PC) (PC) + size (instr);  
IF [cc] THEN (PC) (PC) + rel  
Binary Mode  
Source Mode  
Mnemonic  
<dest>, <src>(1)  
Comments  
Bytes States Bytes States  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
JC  
rel  
rel  
rel  
rel  
rel  
rel  
rel  
rel  
rel  
rel  
Jump if carry  
2
2
3
3
3
3
3
3
3
3
1/4  
1/4  
2/5  
2/5  
2/5  
2/5  
2/5  
2/5  
2/5  
2/5  
2
2
2
2
2
2
2
2
2
2
1/4  
1/4  
1/4  
1/4  
1/4  
1/4  
1/4  
1/4  
1/4  
1/4  
JNC  
JE  
Jump if not carry  
Jump if equal  
JNE  
JG  
Jump if not equal  
Jump if greater than  
JLE  
Jump if less than, or equal  
JSL  
Jump if less than (signed)  
JSLE  
JSG  
JSGE  
Notes:  
Jump if less than, or equal (signed)  
Jump if greater than (signed)  
Jump if greater than or equal (signed)  
1. A shaded cell denotes an instruction in the C51 Architecture.  
2. States are given as jump not-taken/taken.  
3. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.  
25  
Rev. A - May 7, 1999  
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