TSC80251G2D
7.2 Size and Execution Time for Instruction Families
Table 20. Summary of Add and Subtract Instructions
Add
ADD <dest>, <src>
dest opnd ← dest opnd + src opnd
Subtract
Add with Carry
Subtract with Borrow
SUB <dest>, <src>
ADDC <dest>, <src>
SUBB <dest>, <src>
dest opnd ← dest opnd - src opnd
(A) ← (A) + src opnd + (CY)
(A) ← (A) - src opnd - (CY)
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
A, Rn
Register to ACC
1
2
1
2
3
3
3
4
5
5
4
4
5
5
4
4
1
1
2
2
2
2
2
2
2
3
4
4
3
3
4
4
3
3
2
2
(2)
(2)
A, dir8
Direct address to ACC
1
1
ADD
A, @Ri
Indirect address to ACC
2
1
2
3
5
3
4
3
1
1
2
4
2
3
A, #data
Immediate data to ACC
Rmd, Rms
WRjd, WRjs
DRkd, DRks
Rm, #data
WRj, #data16
DRk, #0data16
Rm, dir8
Byte register to/from byte register
Word register to/from word register
Dword register to/from dword register
Immediate 8-bit data to/from byte register
Immediate 16-bit data to/from word register
16-bit unsigned immediate data to/from dword register
Direct address (on-chip RAM or SFR) to/from byte register
Direct address (on-chip RAM or SFR) to/from word register
Direct address (64K) to/from byte register
Direct address (64K) to/from word register
Indirect address (64K) to/from byte register
Indirect address (16M) to/from byte register
Register to/from ACC with carry
6
5
ADD / SUB
(2)
(2)
3
2
WRj, dir8
Rm, dir16
WRj, dir16
Rm, @WRj
Rm, @DRk
A, Rn
4
3
(3)
(3)
3
2
(4)
(3)
(3)
(4)
(3)
(3)
4
3
4
3
2
3
1
2
Direct address (on-chip RAM or SFR) to/from ACC with
carry
(2)
(2)
A, dir8
2
1
2
1
ADDC / SUBB
A, @Ri
A, #data
Indirect address to/from ACC with carry
Immediate data to/from ACC with carry
1
2
2
1
2
2
3
1
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Rev. A - May 7, 1999
18
TEMIC [ TEMIC SEMICONDUCTORS ]
