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TSC80251G2D-24CB 参数 Datasheet PDF下载

TSC80251G2D-24CB图片预览
型号: TSC80251G2D-24CB
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器,串行通信接口 [8/16-bit Microcontroller with Serial Communication Interfaces]
分类和应用: 微控制器外围集成电路异步传输模式ATM通信时钟
文件页数/大小: 63 页 / 813 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
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TSC80251G2D  
Table 21. Summary of Increment and Decrement Instructions  
Increment  
Increment  
Decrement  
Decrement  
INC <dest>  
INC <dest>, <src>  
DEC <dest>  
dest opnd dest opnd + 1  
dest opnd dest opnd + src opnd  
dest opnd dest opnd - 1  
DEC <dest>, <src>  
dest opnd dest opnd - src opnd  
Binary Mode  
Source Mode  
Mnemonic  
<dest>, <src>(1)  
Comments  
Bytes States Bytes States  
A
ACC by 1  
1
1
2
1
3
3
3
3
1
1
1
2
2
2
2
2
2
2
1
1
Rn  
Register by 1  
1
2
INC  
DEC  
(2)  
(2)  
dir8  
Direct address (on-chip RAM or SFR) by 1  
Indirect address by 1  
2
2
@Ri  
3
2
2
4
5
1
4
1
1
3
4
1
Rm, #short  
WRj, #short  
DRk, #short  
DRk, #short  
DPTR  
Byte register by 1, 2, or 4  
INC  
DEC  
Word register by 1, 2, or 4  
Double word register by 1, 2, or 4  
Double word register by 1, 2, or 4  
Data pointer by 1  
INC  
DEC  
INC  
Notes:  
1. A shaded cell denotes an instruction in the C51 Architecture.  
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.  
Table 22. Summary of Compare Instructions  
Compare  
CMP <dest>, <src>  
dest opnd - src opnd  
Binary Mode  
Source Mode  
Mnemonic  
<dest>, <src>(2)  
Comments  
Bytes States Bytes States  
Rmd, Rms  
Register with register  
3
3
3
4
5
5
5
4
4
5
5
4
4
2
3
5
3
4
6
2
2
2
3
4
4
4
3
3
4
4
3
3
1
2
4
2
3
5
WRjd, WRjs  
DRkd, DRks  
Rm, #data  
Word register with word register  
Dword register with dword register  
Register with immediate data  
WRj, #data16  
DRk, #0data16  
DRk, #1data16  
Rm, dir8  
Word register with immediate 16-bit data  
Dword register with zero-extended 16-bit immediate data  
Dword register with one-extended 16-bit immediate data  
Direct address (on-chip RAM or SFR) with byte register  
Direct address (on-chip RAM or SFR) with word register  
Direct address (64K) with byte register  
CMP  
6
5
(1)  
(1)  
3
2
WRj, dir8  
4
3
(2)  
(2)  
Rm, dir16  
3
2
(3)  
(2)  
(2)  
(3)  
(2)  
(2)  
WRj, dir16  
Rm, @WRj  
Rm, @DRk  
Direct address (64K) with word register  
4
3
4
3
2
3
Indirect address (64K) with byte register  
Indirect address (16M) with byte register  
Notes:  
1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.  
2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).  
3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).  
19  
Rev. A - May 7, 1999