TSC80251G2D
Table 26. Summary of Move Instructions (1/3)
Move to High word
Move with Sign extension
Move with Zero extension
Move Code
MOVH <dest>, <src>
MOVS <dest>, <src>
MOVZ <dest>, <src>
MOVC A, <src>
dest opnd
← src opnd
31:16
dest opnd ← src opnd with sign extend
dest opnd ← src opnd with zero extend
(A) ← src opnd
Move eXtended
MOVX <dest>, <src>
dest opnd ← src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(2)
Comments
Bytes States Bytes States
MOVH
MOVS
MOVZ
DRk, #data16
WRj, Rm
16-bit immediate data into upper word of dword register
Byte register to word register with sign extension
Byte register to word register with zeros extension
Code byte relative to DPTR to ACC
5
3
3
1
1
1
1
1
1
3
2
4
2
2
1
1
1
1
1
1
2
1
WRj, Rm
2
1
(3)
(3)
A, @A +DPTR
A, @A +PC
A, @Ri
6
6
MOVC
(3)
(3)
Code byte relative to PC to ACC
6
6
(2)
Extended memory (8-bit address) to ACC
4
5
(2)
(4)
(4)
A, @DPTR
@Ri, A
Extended memory (16-bit address) to ACC
3
3
MOVX
(2)
ACC to extended memory (8-bit address)
4
4
(2)
(3)
(3)
@DPTR, A
ACC to extended memory (16-bit address)
4
4
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. Extended memory addressed is in the region specified by DPXL (reset value= 01h).
3. If this instruction addresses external memory location, add N+1 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
Table 27. Summary of Move Instructions (2/3)
(1)
Move
MOV <dest>, <src>
dest opnd ← src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(2)
Comments
Bytes States Bytes States
A, Rn
Register to ACC
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
2
2
2
2
2
3
3
2
3
3
3
3
2
3
3
3
2
(3)
(3)
A, dir8
Direct address (on-chip RAM or SFR) to ACC
Indirect address to ACC
1
1
A, @Ri
2
1
3
1
A, #data
Rn, A
Immediate data to ACC
ACC to register
1
2
(3)
(3)
Rn, dir8
Rn, #data
dir8, A
Direct address (on-chip RAM or SFR) to register
Immediate data to register
1
2
1
2
(3)
(3)
ACC to direct address (on-chip RAM or SFR)
Register to direct address (on-chip RAM or SFR)
Direct address to direct address (on-chip RAM or SFR)
Indirect address to direct address (on-chip RAM or SFR)
Immediate data to direct address (on-chip RAM or SFR)
ACC to indirect address
2
2
MOV
(3)
(4)
(3)
(3)
(3)
(4)
(3)
(3)
dir8, Rn
dir8, dir8
dir8, @Ri
dir8, #data
@Ri, A
2
3
3
3
3
3
4
3
3
4
(3)
(3)
@Ri, dir8
@Ri, #data
DPTR, #data16
Direct address (on-chip RAM or SFR) to indirect address
Immediate data to indirect address
3
4
3
2
4
2
Load Data Pointer with a 16-bit constant
Notes:
1. Instructions that move bits are in Table 29.
2. Move instructions from the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. Apply note 3 for each dir8 operand.
Rev. A - May 7, 1999
22
TEMIC [ TEMIC SEMICONDUCTORS ]
