TSC80251G2D
Table 28. Summary of Move Instructions (3/3)
(1)
Move
MOV <dest>, <src>
dest opnd ← src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes States Bytes States
Rmd, Rms
WRjd, WRjs
DRkd, DRks
Rm, #data
Byte register to byte register
3
3
3
4
5
5
5
4
4
4
5
5
5
4
4
4
4
4
4
4
5
5
5
4
4
4
4
5
5
5
5
5
5
5
5
2
2
3
3
3
5
2
2
2
3
4
4
4
3
3
3
4
4
4
3
3
3
3
3
3
3
4
4
4
3
3
3
3
4
4
4
4
4
4
4
4
1
1
2
2
2
4
Word register to word register
Dword register to dword register
Immediate 8-bit data to byte register
WRj, #data16
DRk, #0data16
DRk, #1data16
Rm, dir8
Immediate 16-bit data to word register
zero-ext 16bit immediate data to dword register
one-ext 16bit immediate data to dword register
Direct address (on-chip RAM or SFR) to byte register
Direct address (on-chip RAM or SFR) to word register
Direct address (on-chip RAM or SFR) to dword register
Direct address (64K) to byte register
5
4
(3)
(3)
3
2
WRj, dir8
4
3
DRk, dir8
6
5
(4)
(4)
Rm, dir16
3
2
(5)
(6)
(4)
(4)
(5)
(5)
(3)
(5)
(6)
(4)
(4)
(5)
(5)
(3)
WRj, dir16
DRk, dir16
Rm, @WRj
Rm, @DRk
WRjd, @WRjs
WRj, @DRk
dir8, Rm
Direct address (64K) to word register
4
6
3
4
4
5
4
3
5
2
3
3
4
3
Direct address (64K) to dword register
Indirect address (64K) to byte register
Indirect address (16M) to byte register
Indirect address (64K) to word register
Indirect address (16M) to word register
Byte register to direct address (on-chip RAM or SFR)
Word register to direct address (on-chip RAM or SFR)
Dword register to direct address (on-chip RAM or SFR)
Byte register to direct address (64K)
MOV
dir8, WRj
5
4
dir8, DRk
7
6
(4)
(4)
dir16, Rm
4
3
(5)
(6)
(4)
(4)
(5)
(5)
(4)
(5)
(4)
(5)
(4)
(5)
(4)
(5)
(5)
(6)
(4)
(4)
(5)
(5)
(4)
(5)
(4)
(5)
(4)
(5)
(4)
(5)
dir16, WRj
dir16, DRk
@WRj, Rm
@DRk, Rm
@WRjd, WRjs
@DRk, WRj
Word register to direct address (64K)
5
7
4
5
5
6
6
7
7
8
6
7
7
8
4
6
3
4
4
5
5
6
6
7
5
6
6
7
Dword register to direct address (64K)
Byte register to indirect address (64K)
Byte register to indirect address (16M)
Word register to indirect address (64K)
Word register to indirect address (16M)
Rm, @WRj +dis16 Indirect with 16-bit displacement (64K) to byte register
WRj, @WRj +dis16 Indirect with 16-bit displacement (64K) to word register
Rm, @DRk +dis24 Indirect with 16-bit displacement (16M) to byte register
WRj, @WRj +dis24 Indirect with 16-bit displacement (16M) to word register
@WRj +dis16, Rm Byte register to indirect with 16-bit displacement (64K)
@WRj +dis16, WRj Word register to indirect with 16-bit displacement (64K)
@DRk +dis24, Rm Byte register to indirect with 16-bit displacement (16M)
@DRk +dis24, WRj Word register to indirect with 16-bit displacement (16M)
Notes:
1. Instructions that move bits are in Table 29.
2. Move instructions unique to the C251 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states).
23
Rev. A - May 7, 1999
TEMIC [ TEMIC SEMICONDUCTORS ]
