TSC80251G2D
UCONFIG1
Configuration Byte 1
7
6
5
-
4
3
2
1
0
CSIZE
-
INTR
WSB
WSB1#
WSB0#
EMAP#
Bit Number Bit Mnemonic
Description
(1)
On-Chip Code Memory Size bit
CSIZE
TSC87251G2D
Clear to select 16 Kbytes of on-chip code memory (TSC87251G1D product).
Set to select 32 Kbytes of on-chip code memory (TSC87251G2D product).
7
-
Reserved
Set this bit when writing to UCONFIG1.
TSC80251G2D
TSC83251G2D
Reserved
Set this bit when writing to UCONFIG1.
6
5
-
-
Reserved
Set this bit when writing to UCONFIG1.
(2)
Interrupt Mode bit
Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register).
Set so that the interrupts push four bytes onto the stack (the three bytes of the PC register and the
PSW1 register).
4
3
2
INTR
WSB
(3)
Wait State B bit
Clear to generate one wait state for memory region 01:.
Set for no wait states for memory region 01:.
Wait State B bits
Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses
(only region 01:).
WSB1#
WSB1#
WSB0#
Number of Wait States
0
0
1
1
0
1
0
1
3
2
1
0
1
0
WSB0#
EMAP#
On-Chip Code Memory Map bit
Clear to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data
space (at 00:C000h-00:FFFFh).
Set not to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data
space.
Notes:
1. The CSIZE is only available on EPROM/OTPROM products.
2. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used
with code executing outside region FF:.
3. Use only for Step A compatibility; set this bit when WSB1:0# are used.
Figure 8. Configuration Byte 1
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals
RD1
RD0
P1.7
P3.7/RD#
PSEN#
WR#
External Memory
Read signal for all external Write signal for all external
memory locations memory locations
0
0
A17
A16
256 Kbytes
Read signal for all external Write signal for all external
memory locations memory locations
0
1
1
1
0
1
I/O pin
I/O pin
I/O pin
A16
128 Kbytes
64 Kbytes
Read signal for all external Write signal for all external
memory locations memory locations
I/O pin
Read signal for regions 00: Read signal for regions FE: Write signal for all external
and 01: and FF: memory locations
(1)
2 × 64 Kbytes
Note:
1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code.
Rev. A - May 7, 1999
15
TEMIC [ TEMIC SEMICONDUCTORS ]
