TSC87251G1A
Table 33. Summary of unconditional Jump Instructions
Absolute jump
Extended jump
Long jump
Short jump
Jump indirect
No operation
AJMP <src>
EJMP <src>
LJMP <src>
SJMP rel
JMP @A +DPTR
NOP
(PC) ← (PC) +2; (PC)
(PC) ← (PC) + size (instr); (PC)
(PC) ← (PC) + size (instr); (PC)
← src opnd
10:0
← src opnd
← src opnd
23:0
15:0
(PC) ← (PC) +2; (PC) ← (PC) +rel
(PC) ← FFh; (PC) ← (A) + (DPTR)
23:16
15:0
(PC) ← (PC) +1
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes
States
Bytes
States
(2)(3)
(2)(3)
AJMP
EJMP
addr11
addr24
@DRk
@WRj
addr16
rel
Absolute jump
Extended jump
2
5
3
3
3
2
1
1
3
2
4
2
2
3
2
1
1
3
(2)(4)
(2)(4)
6
5
(2)(4)
(2)(4)
Extended jump (indirect)
Long jump (indirect)
7
6
(2)(4)
(2)(4)
6
5
LJMP
(2)(4)
(2)(4)
Long jump (direct address)
Short jump (relative address)
Jump indirect relative to the DPTR
No operation (Jump never)
5
5
(2)(4)
(2)(4)
SJMP
JMP
4
4
(2)(4)
(2)(4)
@A +DPTR
5
5
NOP
1
1
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 3 to the number of states if the destination address is external.
Table 34. Summary of Call and Return Instructions
Absolute call
Extended call
Long call
ACALL <src>
ECALL <src>
LCALL <src>
(PC) ← (PC) +2; push (PC)
;
15:0
(PC)
← src opnd
10:0
(PC) ← (PC) + size (instr); push (PC)
;
;
23:0
15:0
(PC)
← src opnd
23:0
(PC) ← (PC) + size (instr); push (PC)
(PC)
← src opnd
15:0
Return from subroutine
Extended return from subroutine
Return from interrupt
RET
ERET
RETI
pop (PC)
pop (PC)
IF [INTR= 0] THEN pop (PC)
15:0
23:0
15:0
IF [INTR= 1] THEN pop (PC) ; pop (PSW1)
23:0
Trap interrupt
TRAP
(PC) ← (PC) + size (instr);
IF [INTR= 0] THEN push (PC)
15:0
IF [INTR= 1] THEN push (PSW1); push (PC)
23:0
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(1)
Comments
Bytes
States
Bytes
States
(2)(3)
(2)(3)
ACALL
ECALL
addr11
@DRk
addr24
@WRj
addr16
Absolute subroutine call
Extended subroutine call (indirect)
Extended subroutine call
Long subroutine call (indirect)
Long subroutine call
2
3
5
3
3
1
3
1
2
9
2
2
4
2
3
1
2
1
1
9
(2)(3)
(2)(3)
14
13
(2)(3)
(2)(3)
14
13
(2)(3)
(2)(3)
10
9
LCALL
(2)(3)
(2)(3)
9
9
(2)
(2)
RET
Return from subroutine
7
7
(2)
(2)
ERET
RETI
TRAP
Extended subroutine return
Return from interrupt
9
8
(2)(4)
(2)(4)
7
7
(4)
(4)
Jump to the trap interrupt vector
12
11
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination/return address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 5 to the number of states if INTR= 1.
26
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
