TSC87251G1A
Table 37. Signature Bytes (Electronic ID)
Signature Address
Signature Data
Vendor
TEMIC
30h
31h
60h
61h
58h
40h
FBh
FFh
Architecture
Memory
Revision
C251
16K EPROM/OTPROM
First (TSC8x251G1A)
8.3. Programming Algorithm
Figure 8 shows the hardware setup needed to program the TSC87251G1A EPROM areas:
D The chip has to be put under reset and maintained in this state until the completion of the programming sequence.
D PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
D Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state
until the completion of the programming sequence (see below).
D The voltage on the EA# pin must be set to VDD.
D The programming mode is selected according to the code applied on Port 0 (see Table 38). It has to be applied until
the completion of this programming operation.
D The programming address is applied on Ports 1 and 3 which are respectively the Most Significant Byte (MSB) and
the Least Significant Byte (LSB) of the address.
D The programming data are applied on Port 2.
D The EPROM Programming is done by raising the voltage on the EA# pin to VPP, then by generating a low level
pulse on ALE/PROG# pin.
D The voltage on the EA# pin must be lowered to VDD before completing the programming operation.
D It is possible to alternate programming and verifying operation (See paragraph 8.4.). Please make sure the voltage
on the EA# pin has actually been lowered to VDD before performing the verifying operation.
D PSEN# and the other control signals have to be released to complete a sequence of programming operations or a
sequence of programming and verifying operations.
VDD
VDD
VDD
RST
EA#/VPP
ALE/PROG#
PSEN#
VPP
100 µs pulses
Mode
A[7:0]
A[13:8]
Data
P0[7:0]
TSC87251G1A
P3[7:0]
P1[7:0]
P2[7:0]
4 to 12 MHz
XTAL1
VSS/VSS1/VSS2
Figure 8. Setup for EPROM Programming
29
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
