TSC87251G1A
Table 38. Programming Modes
ROM Area(1)
RST
EA#/VPP PSEN# ALE/PROG#(2)
P0
P2
P1(MSB) P3(LSB)
On–chip Code Memory
1
VPP
VPP
VPP
0
0
0
1 Pulse
1 Pulse
1 Pulse
68h
Data
16–bit Address
0000h-3FFFh (16K)
Configuration Bytes
Lock Bits
1
1
69h
Data
X
CONFIG0: 0080h
CONFIG1: 0081h
6Bh
LB0: 0001h
LB1: 0002h
LB2: 0003h
Encryption Array
1
VPP
0
1 Pulse
6Ch
Data
0000h-007Fh
Notes:
1. Signature Bytes are not user–programmable.
2. The ALE/PROG# pulse waveform is shown in Figure 24 page 46.
8.4. Verify Algorithm
Figure 9 shows the hardware setup needed to verify the TSC87251G1A EPROM areas:
D The chip has to be put under reset and maintained in this state until the completion of the verifying sequence.
D PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
D Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state
until the completion of the verifying sequence (see below).
D The voltage on the EA# pin must be set to VDD and ALE must be set to a high level.
D The Verifying Mode is selected according to the code applied on Port 0. It has to be applied until the completion of
this verifying operation.
D The verifying address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address.
D Then device is driving the data on Port 2.
D It is possible to alternate programming and verification operation (see paragraph 8.3.). Please make sure the voltage
on the EA# pin has actually been lowered to VDD before performing the verifying operation.
D PSEN# and the other control signals have to be released to complete a sequence of verifying operations or a
sequence of programming and verifying operations.
Table 39. Verifying Modes
ROM Area(1)
RST
EA#/VPP PSEN# ALE/PROG#
P0
P2
P1(MSB) P3(LSB)
On–chip code memory
1
1
0
1
28h
Data
16–bit Address
0000h-3FFFh (16K)
Configuration Bytes
1
1
0
1
29h
Data
CONFIG0: 0080h
CONFIG1: 0081h
Lock Bits
1
1
1
1
0
0
1
1
2Bh
29h
Data
Data
0000h
Signature Bytes
0030h, 0031h, 0060h, 0061h
Note:
1. To preserve the secrecy of on–chip code memory when encypted, the Encryption Array can not be verified.
30
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
