TSC87251G1A
Table 30. Summary of Exchange, Push and Pop Instructions
Exchange bytes
Exchange Digit
Push
XCH A, <src>
XCHD A, <src>
PUSH <src>
(A) $ src opnd
(A) src opnd
(SP) ← (SP) +1; ((SP)) ← src opnd;
(SP) ← (SP) + size (src opnd) – 1
$
3:0
3:0
Pop
POP <dest>
(SP) ← (SP) – size (dest opnd) + 1;
dest opnd ← ((SP)); (SP) ← (SP) –1
Binary Mode
Source Mode
Mnemonic
XCH
<dest>, <src>(1)
Comments
Bytes
States
Bytes
States
A, Rn
A, dir8
A, @Ri
A, @Ri
dir8
ACC and register
1
2
1
1
2
4
3
2
2
2
2
2
3
4
(3)
(3)
ACC and direct address (on–chip RAM or SFR)
ACC and indirect address
3
3
4
4
5
5
XCHD
ACC low nibble and indirect address (256 bytes)
Push direct address onto stack
(2)
(2)
2
2
#data
Push immediate data onto stack
4
5
4
5
9
3
5
3
4
8
#data16
Rm
Push 16-bit immediate data onto stack
Push byte register onto stack
5
3
3
3
2
3
3
3
4
2
2
2
2
2
2
2
PUSH
WRj
DRk
dir8
Push word register onto stack
Push double word register onto stack
Pop direct address (on–chip RAM or SFR) from stack
Pop byte register from stack
(2)
(2)
3
3
Rm
3
5
9
2
4
8
POP
WRj
DRk
Pop word register from stack
Pop double word register from stack
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 31. Summary of Conditional Jump Instructions (1/2)
Jump conditional on status
Jcc rel
(PC) ← (PC) + size (instr);
IF [cc] THEN (PC) ← (PC) + rel
Binary Mode(2)
Source Mode(2)
Mnemonic
<dest>, <src>(1)
Comments
Bytes
States
Bytes
States
(3)
(3)
JC
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
Jump if carry
2
2
3
3
3
3
3
3
3
3
1/4
2
2
2
2
2
2
2
2
2
2
1/4
(3)
(3)
JNC
JE
Jump if not carry
Jump if equal
1/4
1/4
(3)
(3)
2/5
1/4
(3)
(3)
JNE
JG
Jump if not equal
Jump if greater than
2/5
1/4
(3)
(3)
2/5
1/4
(3)
(3)
JLE
JSL
JSLE
JSG
JSGE
Jump if less than, or equal
2/5
1/4
(3)
(3)
Jump if less than (signed)
2/5
1/4
(3)
(3)
Jump if less than, or equal (signed)
Jump if greater than (signed)
Jump if greater than or equal (signed)
2/5
1/4
(3)
(3)
2/5
1/4
(3)
(3)
2/5
1/4
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.
24
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
