TSC87251G1A
Table 28. Summary of Move Instructions (3/3)
(1)
Move
MOV <dest>, <src>
dest opnd ← src opnd
Binary Mode
Source Mode
Mnemonic
<dest>, <src>(2)
Comments
Bytes
3
States
Bytes
2
States
Rmd, Rms
Byte register to byte register
2
2
3
3
3
5
5
1
1
2
2
2
4
4
WRjd, WRjs
DRkd, DRks
Rm, #data
Word register to word register
3
2
Dword register to dword register
3
2
Immediate 8-bit data to byte register
Immediate 16-bit data to word register
zero-ext 16bit immediate data to dword register
one-ext 16bit immediate data to dword register
Direct address to byte register
4
3
WRj, #data16
DRk, #0data16
DRk, #1data16
Rm, dir8
5
4
5
4
5
4
(3)
(3)
4
3
3
2
WRj, dir8
Direct address to word register
4
4
6
3
3
5
DRk, dir8
Direct address to dword register
4
3
(4)
(4)
Rm, dir16
Direct address (64K) to byte register
Direct address (64K) to word register
Direct address (64K) to dword register
Indirect address (64K) to byte register
Indirect address (16M) to byte register
Indirect address (64K) to word register
Indirect address (16M) to word register
Byte register to direct address
5
3
4
2
(5)
(5)
WRj, dir16
5
4
4
3
(6)
(6)
DRk, dir16
5
6
4
5
(4)
(4)
Rm, @WRj
4
3
3
2
(4)
(4)
Rm, @DRk
4
4
3
3
(5)
(5)
WRjd, @WRjs
WRj, @DRk
dir8, Rm
4
4
3
3
(5)
(5)
4
5
3
4
(3)
(3)
4
4
3
3
dir8, WRj
Word register to direct address
4
5
7
3
4
6
MOV
dir8, DRk
Dword register to direct address
4
3
(4)
(4)
dir16, Rm
Byte register to direct address (64K)
Word register to direct address (64K)
Dword register to direct address (64K)
Byte register to indirect address (64K)
Byte register to indirect address (16M)
Word register to indirect address (64K)
Word register to indirect address (16M)
Indirect with 16–bit dis (64K) to byte register
Indirect with 16–bit dis (64K) to word register
Indirect with 16–bit dis (16M) to byte register
Indirect with 16–bit dis (16M) to word register
Byte register to indirect with 16–bit dis (64K)
Word register to indirect with 16–bit dis (64K)
Byte register to indirect with 16–bit dis (16M)
Word register to indirect with 16–bit dis (16M)
5
4
4
3
(5)
(5)
dir16, WRj
5
5
4
4
(6)
(6)
dir16, DRk
5
7
4
6
(4)
(4)
@WRj, Rm
4
4
3
3
(4)
(4)
@DRk, Rm
4
5
3
4
(5)
(5)
@WRjd, WRjs
@DRk, WRj
Rm, @WRj +dis16
WRj, @WRj +dis16
Rm, @DRk +dis24
WRj, @WRj +dis24
@WRj +dis16, Rm
@WRj +dis16, WRj
@DRk +dis24, Rm
@DRk +dis24, WRj
4
5
3
4
(5)
(5)
4
6
3
5
(4)
(4)
5
6
4
5
(5)
(5)
5
7
4
6
(4)
(4)
5
7
4
6
(5)
(5)
5
8
4
7
(4)
(4)
5
6
4
5
(5)
(5)
5
7
4
6
(4)
(4)
5
7
4
6
(5)
(5)
5
8
4
7
Notes:
1. Instructions that move bits are in Table 29.
2. Move instructions unique to the C251 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states).
22
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
