ICM-20602
9.36 REGISTER 106 – USER CONTROL
Register Name: USER_CTRL
Register Type: READ/WRITE
Register Address: 106 (Decimal); 6A (Hex)
BIT
[7]
NAME
-
FUNCTION
Reserved
1 – Enable FIFO operation mode.
0 – Disable FIFO access from serial interface.
[6]
FIFO_EN
[5]
[4]
[3]
-
-
-
Reserved
Reserved
Reserved
1 – Reset FIFO module. Reset is asynchronous. This bit auto clears after one clock cycle of
the internal 20 MHz clock.
Reserved
[2]
[1]
[0]
FIFO_RST
-
1 – Reset all gyro digital signal path, accel digital signal path, and temp digital signal path.
This bit also clears all the sensor registers.
SIG_COND_RST
9.37 REGISTER 107 – POWER MANAGEMENT 1
Register Name: PWR_MGMT_1
Register Type: READ/WRITE
Register Address: 107 (Decimal); 6B (Hex)
BIT
[7]
[6]
NAME
FUNCTION
1 – Reset the internal registers and restores the default settings. The bit automatically clears
to 0 once the reset is done.
When set to 1, the chip is set to sleep mode.
DEVICE_RESET
SLEEP
When set to 1, and SLEEP and STANDBY are not set to 1, the chip will cycle between sleep
and taking a single accelerometer sample at a rate determined by SMPLRT_DIV
NOTE: When all accelerometer axes are disabled via PWR_MGMT_2 register bits and cycle is enabled,
the chip will wake up at the rate determined by the respective registers above, but will not take any
samples.
[5]
CYCLE
When set, the gyro drive and pll circuitry are enabled, but the sense paths are disabled. This
is a low power mode that allows quick enabling of the gyros.
When set to 1, this bit disables the temperature sensor.
Code Clock Source
[4]
[3]
GYRO_STANDBY
TEMP_DIS
0
1
Internal 20 MHz oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal
oscillator
2
3
4
5
Auto selects the best available clock source – PLL if ready, else use the Internal
oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal
oscillator
[2:0]
CLKSEL[2:0]
Auto selects the best available clock source – PLL if ready, else use the Internal
oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal
oscillator
Internal 20 MHz oscillator
6
7
Stops the clock and keeps timing generator in reset
NOTE: The default value of CLKSEL[2:0] is 001. It is required that CLKSEL[2:0] be set to 001 to achieve full gyroscope performance.
Document Number: DS-000176
Revision: 1.0
Page 46 of 57
Revision Date: 10/03/2016
TDK [ TDK ELECTRONICS ]
