SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
14.4
IIC Address2 Register( IICA2 )
Mnemonic: IICA2
Address: FB
7
6
5
4
3
2
1
0
Reset
IICA2[7:1]
Match2 or RW2 60H
R/W
R or R/W
Slave mode:
IICA2[7:1]: IIC Address registers
This is the second 7-bit address for this slave module.
It will be checked when an address (from master) is received
Match2:
When IICA2 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets first data, this bit will clear.
Master mode:
IICA2[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW2:
This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It is
used to tell the salve the direction of the following communication. If it is 1, the module is in
master receive mode. If 0, the module is in master transmit mode.
RW2=1, master receive mode
RW2=0, master transmit mode
14.5
IIC Read Write Register( IICRWD )
Mnemonic: IICRWD
Address: FCh
7
6
5
4
3
2
1
0
Reset
00h
IICRWD[7:0]
IICRWD[7:0]: IIC read write data buffer.
In receiving (read) mode, the received byte is stored here.
In transmitting mode, the byte to be shifted out through SDA stays here.
14.6
IIC Enable Bus Transaction Register( IICEBT )
Mnemonic: IICEBT
Address: FDH
Reset
7
6
5
-
4
-
3
-
2
-
1
-
0
-
FU_EN
Master Mode：
00: reserved
00H
01: IIC bus module will enable read/write data transfer on SDA and SCL.
10: IIC bus module generate a start condition on the SDA/SCL, then send out
address which is stored in the IICA1/IICA2(selected by MAS control bit)
11: IIC bus module generates a stop condition on the SDA/SCL.
FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6] repeatedly
is necessary.
Slave mode:
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 101 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
