SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
Mnemonic: AUX
Address: 91h
7
6
-
5
4
3
2
1
-
0
DPS
Reset
00H
BRGS
P4SPI
P4UR1
P4IIC
P0KBI
P4SPI: P4SPI = 0 – SPI function on P1.
P4SPI = 1 – SPI function on P4.
15.1
SPI Control Register 1( SPIC1 )
Mnemonic:SPIC1
Address:F1H
7
6
5
4
3
2
1
0
Reset
08H
SPIEN SPIMSS SPISSP SPICKP SPICKE
SPIBR[2:0]
SPIEN: Enable SPI module.
SPIEN = 1 - is Enable.
SPIEN = 0 - is Disable.
SPIMSS: Master or Slave mode Select
SPIMSS = 1 - is Master mode.
SPIMSS = 0 - is Slave mode.
SPISSP: SS or CS active polarity.(Slave mode used only)
SPISSP = 1 - high active.
SPISSP = 0 - low active.
SPICKP: Clock idle polarity select. (Master mode used only)
SPICKP = 1 - SCK will idle high. Ex :
SPICKP = 0 - SCK will idle low. Ex :
SPICKE: Clock sample edge select.
SPICKE = 1 - rising edge latch data.
SPICKE = 0 - falling edge latch data.
* To ensure the data latch stability, SM59A16U1 generate the output data As shown in
the following example, the other side can latch the stable data no matter in rising or
falling edge.
sufficient set-up time
sufficient hold time
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 104 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
