SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
14. IIC function
The IIC module uses the SCL (clock) and the SDA (data) line to communicate with external IIC interface. Its speed can
be selected to 400Kbps (maximum) by software setting the IICBR [2:0] control bit. The IIC module provided 2 interrupts
(RXIF, TXIF). It will generate START, repeated START and STOP signals automatically in master mode and can
detects START, repeated START and STOP signals in slave mode. The maximum communication length and the
number of devices that can be connected are limited by a maximum bus capacitance of 400pF.
The interrupt vector is 6Bh.
Mnemonic
Description
Dir.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
IIC function
P4UR
1
AB_E
N
AUX
IICCTL
IICS
Auxiliary register
91h
F9h
F8h
BRGS
-
P4SPI
MAS
LAIF
P4IIC
BF_EN
TXIF
P0KBI
-
DPS
00H
04H
00H
IIC control
register
IICEN
-
MSS
MPIF
IICBR[2:0]
RXAK TXAK
RW or
BB
IIC status register
RXIF
MATC
H1or
RW1
MATC
H2 or
RW2
IIC Address 1
register
IICA1
IICA2
FAh
FBh
IICA1[7:1]
A0H
60H
IIC Address 2
register
IICA2[7:1]
IIC Read/Write
register
IIC Enaable Bus
Transaction
IICRWD
IICEBT
FCh
FDh
IICRWD[7:0]
00H
00H
FU_EN
-
-
-
-
-
-
Mnemonic: AUX
Address: 91h
7
6
-
5
4
3
2
1
-
0
DPS
Reset
00H
BRGS
P4SPI
P4UR1
P4IIC
P0KBI
P4IIC: P4IIC = 0 – IIC function on P1.
P4IIC = 1 – IIC function on P4.
14.1
IIC Control Register( IICCTL )
Mnemonic: IICCTL
Address: F9h
7
6
MSS
5
MAS
4
3
2
1
0
Reset
04h
IICEN
AB_EN
BF_EN
IICBR[2:0]
IICEN: Enable IIC module
IICEN = 1 is Enable
IICEN = 0 is Disable.
MSS: Master or slave mode select.
MSS = 1 is master mode.
MSS = 0 is slave mode.
*The software must set this bit before setting others register.
MAS: Master address select (master mode only)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 97 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
