SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
set (NoAck) or clear (Ack) and transmit to master to indicate the receive status.
RW or BB: Master Mode:
BB : Bus busy bit
If detect scl=0 or sda=0 or bus start, this bit will be set. If detect stop,this bit will be
cleared. This bit can be cleared by software to return ready state.
Slave Mode:
RW:The slave mode read (received) or wrote (transmit) on the IIC bus. When this bit is
clear, the slave module received data on the IIC bus (SDA).(Slave mode only).
As shown in Fig. 14-1
Fig. 14-1: Acknowledgement bit in the 9th bit of a byte transmission
14.3
IIC Address1 Register( IICA1 )
Mnemonic: IICA1
Address: FA
7
6
5
4
3
2
1
0
Reset
IICA1[7:1]
Match1 or RW1 A0H
R/W
R or R/W
Slave mode:
IICA1[7:1]: IIC Address registers
This is the first 7-bit address for this slave module. It will be checked when an address (from
master) is received
Match1:
When IICA1 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets first data, this bit will clear.
Master mode:
IICA1[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW1:
This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It
appears at the 8th bit after the IIC address as below figure. It is used to tell the salve the
direction of the following communication. If it is 1, the module is in master receive mode. If 0, the
module is in master transmit mode. As shown in Fig. 14-2
RW1=1, master receive mode
RW1=0, master transmit mode
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
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SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
