欢迎访问ic37.com |
会员登录 免费注册
发布采购

OB59A16U1U48VP 参数 Datasheet PDF下载

OB59A16U1U48VP图片预览
型号: OB59A16U1U48VP
PDF下载: 下载PDF文件 查看货源
内容描述: SM59A16U1 8位微控制器 64KB具有ISP闪存 & 6K + 256B RAM嵌入式 [SM59A16U1 8-Bit Micro-controller 64KB with ISP Flash & 6K+256B RAM embedded]
分类和应用: 闪存微控制器
文件页数/大小: 146 页 / 4372 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
 浏览型号OB59A16U1U48VP的Datasheet PDF文件第94页浏览型号OB59A16U1U48VP的Datasheet PDF文件第95页浏览型号OB59A16U1U48VP的Datasheet PDF文件第96页浏览型号OB59A16U1U48VP的Datasheet PDF文件第97页浏览型号OB59A16U1U48VP的Datasheet PDF文件第99页浏览型号OB59A16U1U48VP的Datasheet PDF文件第100页浏览型号OB59A16U1U48VP的Datasheet PDF文件第101页浏览型号OB59A16U1U48VP的Datasheet PDF文件第102页  
SM59A16U1  
8-Bit Micro-controller  
64KB with ISP Flash  
& 6K+256B RAM embedded  
MAS = 0 is to use IICA1.  
MAS = 1 is to use IICA2.  
AB_EN: Arbitration lost enable bit. (Master mode only)  
If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred,  
hardware will return to IDLE state. If this bit is cleared, hardware will not care arbitration lost  
condition. Set this bit when multi-master and slave connection. Clear this bit when single  
master to single slave.  
BF_EN: Bus busy enable bit. (Master mode only)  
If set BF_EN bit, hardware will not generate a start condition to bus until BF=0. Clear this bit  
will always generate a start condition to bus when MStart is set. Set this bit when multi-master  
and slave connection. Clear this bit when single master to single slave.  
IICBR[2:0]: Baud rate selection (master mode only), where Fosc is the external crystal or oscillator  
frequency. The default is Fosc/512 for users‟ convenience.  
IICBR[2:0]  
000  
Baud rate  
Fosc/32  
001  
Fosc/64  
010  
011  
100  
101  
110  
111  
Fosc/128  
Fosc/256  
Fosc/512  
Fosc/1024  
Fosc/2048  
Fosc/4096  
14.2  
IIC Status Register( IICS )  
Mnemonic: IICS  
Address: F8H  
7
-
6
5
LAIF  
4
3
TXIF  
2
1
0
Reset  
00H  
MPIF  
RXIF  
RXAK  
TxAK  
RW or BB  
MPIF: The Stop condition Interrupt Flag  
The stop condition occurred and this bit will be set. Software need to clear this bit  
LAIF: Arbitration lost bit. (Master mode only)  
The Arbitration Interrupt Flag, the bus arbitration lost occurred and this bit will be set.  
Software need to clear this bit  
RxIF: The data Receive Interrupt Flag (RXIF) is set after the IICRWD (IIC Read Write Data  
Buffer) is loaded with a newly receive data.  
TxIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the IICRWD (IIC Read  
Write Data Buffer) is downloaded to the shift register.  
RxAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has  
been received after the complete 8 bits data transmit on the bus.  
TxAK: The Acknowledge status transmit bit. When received complete 8 bits data, this bit will  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
ISSFD-M071 Ver A SM59A16U1 04/12/2013  
- 98 -  
 复制成功!