SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
SPIBR[2:0]: SPI baud rate select. (Master mode used only)
SPIBR[2:0]
0:0:0
Baud rate
Fosc/4
0:0:1
Fosc /8
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Fosc /16
Fosc /32
Fosc /64
Fosc /128
Fosc /256
Fosc /512
15.2
SPI Control Register 2( SPIC2 )
Mnemonic: SPIC2
Address: F2H
7
6
5
4
3
2
1
0
Reset
SPIFD
TBC[2:0]
SPIRST
RBC[2:0]
00H
SPIFD: Full-duplex mode enable.
SPIFD = 1 is enable full-duplex mode.
SPIFD = 0 is disable full-duplex mode.
When it is set, the TBC[2:0] and RBC[2:0] will be reset and keep to zero. When the Master
device transmits data to the Slave device via the MOSI line, the Slave device responds by
sending data to the Master device via the MISO line. This implies full-duplex transmission with
both data out and data in synchronized with the same clock. As shown in Fig. 15-2
MISO
MISO
Input Shift register
SPIRXD
Output Shift register
SPITXD
MOSI
SCK
MOSI
SCK
Output Shift register
SPITXD
Input Shift register
SPIRXD
Clock Generator
SyncMos Slave
SyncMos Master
Fig. 15-2: SPI Mater and slave transfer method
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 105 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
