SMD1102 / 1103 / 1113
SCL
SDA
1
0
0
1
E/C CH1 CH0 R/M
0
0
0
0
CH1 CH0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
N
A
C
K
S
T
A
R
T
A
C
K
A
C
K
S
T
O
P
Channel
Address
Channel
Address
Echo
Device Type
Identifier
2033 Fig02
Figure 2. Single Channel Read Sequence
Conversion #1
Conversion #2
SCL
SDA
1
0
0
1
E/C CH1 CH0 R/M
0
0
0
0
CH1 CH0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
CH1 CH0 D9 D8
D7 D6
S
T
A
R
T
A
C
K
A
C
K
A
C
K
A
C
K
Channel
Address
Channel
Address
Echo
Channel
Address
Device Type
Identifier
2033 Fig03 3.0
Figure 3. Single Channel Continuous Read Sequence
Conversion #1
Channel 0
Conversion #2
Channel 1
SCL
SDA
1
0
0
1
E/C CH1 CH0 R/M
0
0
0
0
CH1 CH0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
CH1 CH0 D9 D8
D7 D6
S
T
A
R
T
A
C
K
A
C
K
A
C
K
A
C
K
Channel
Address
= 11
Channel 0
Address
Echo
Channel 1
Address
Device Type
Identifier
2033 Fig04
Figure 4. Auto-Increment Continuous Read Sequence
SCL
SDA
1
0
0
1
E/C CH1 CH0 R/M
0
0
0
0
U/L OP0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
S
A
C
K
A
C
K
A
C
K
S
T
Monitor
Option
Upper/Lower
T
A
R
T
Channel
Address
O
P
Device Type
Identifier
2033 Fig05
Figure 5. Programming the Auto-Monitor Limit Registers
SCL
SDA
1
0
0
1
1
CH1 CH0 R/M
0
0
OP0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
1
CH1 CH0
S
A
C
K
A
C
K
A
C
K
Monitor
Option
Lower Limit
T
A
R
T
0
Upper Limit
1
OP0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
1
CH1 CH0
A
C
K
N
A
C
K
S
T
O
P
Monitor
Option
2033 Fig06
Figure 6. Reading the Auto-Monitor Limit Registers
SUMMIT MICROELECTRONICS, Inc.
2033 8.1 10/04/01
7
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
