SMD1102 / 1103 / 1113
SCL
SDA
S
T
A
R
T
1
0
0
1
E/C CH1 CH0 R/M
Channel
Address
A
C
K
0
0
0
0 CH1 CH0 D9
Channel
Address
Echo
D8
A
C
K
D7
D6
D5
D4
D3
D2
D1
D0
N
A
C
K
S
T
O
P
Device Type
Identifier
2033 Fig02
Figure 2. Single Channel Read Sequence
Conversion #1
SCL
SDA
S
T
A
R
T
1
0
0
1
E/C CH1 CH0 R/M
0
0
0
0 CH1 CH0 D9
D8
D7 D6
D5
D4
D3
D2
D1
D0
0
0
0
0 CH1 CH0 D9
D8
D7 D6
Conversion #2
Device Type
Identifier
Channel
Address
A
C
K
Channel
Address
Echo
A
C
K
A
C
K
Channel
Address
A
C
K
2033 Fig03 3.0
Figure 3. Single Channel Continuous Read Sequence
Conversion #1
Channel 0
SCL
SDA
S
T
A
R
T
1
0
0
1
E/C CH1 CH0 R/M
0
0
0
0 CH1 CH0 D9
D8
D7 D6
D5
D4
D3
D2
D1
D0
0
0
0
0 CH1 CH0 D9
D8
D7 D6
Conversion #2
Channel 1
Device Type
Identifier
Channel
Address
= 11
A
C
K
Channel 0
Address
Echo
A
C
K
A
C
K
Channel 1
Address
A
C
K
2033 Fig04
Figure 4. Auto-Increment Continuous Read Sequence
SCL
SDA
S
T
A
R
T
1
0
0
1
E/C CH1 CH0 R/M
Channel
Address
A
C
K
0
0
0
0
U/L OP0 D9
Monitor
Option
D8
A
C
K
D7
D6
D5
D4
D3
D2
D1
D0
A
C
K
S
T
O
P
Upper/Lower
Device Type
Identifier
2033 Fig05
Figure 5. Programming the Auto-Monitor Limit Registers
SCL
SDA
S
T
A
R
T
1
0
0
1
1
CH1 CH0 R/M
A
C
K
1
CH1 CH0
0
0
OP0 D9
Monitor
Option
D8
A
C
K
D7
D6
D5
D4
D3
D2
D1
D0
A
C
K
Lower Limit
1
CH1 CH0
0
1
OP0 D9
Monitor
Option
D8
A
C
K
D7
D6
D5
D4
D3
D2
D1
D0
N
A
C
K
S
T
O
P
Upper Limit
2033 Fig06
Figure 6. Reading the Auto-Monitor Limit Registers
SUMMIT MICROELECTRONICS, Inc.
2033 8.1 10/04/01
7
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
