SMD1102 / 1103 / 1113
BUS INTERFACE
GENERAL DESCRIPTION
The I2C bus is a two-way, two-line serial communication connectedtoapositivesupplybyapull-upresistorlocated
between different integrated circuits. The two lines are: a on the bus. Summit parts have a Schmitt input on both
serial Data line (SDA) and a serial Clock line (SCL). All lines. SeeFigure11andTable2forwaveformsandtiming
Summit Microelectronics parts support a 100kHz clock on the bus. One bit of Data is transferred during each
rate, and some support the alternative 400kHz clock. Clockpulse. TheDatamustremainstablewhentheClock
Check Table 2 for the value of fSCL. The SDA line must be is high.
t
t
LOW
HIGH
t
t
R
F
SCL
t
t
t
t
SU:STO
t
HD:DAT
SU:STA
SU:DAT
HD:STA
t
BUF
SDA In
SDA Out
t
t
AA
DH
2033 Fig11
Figure 11. Interface Bus Timing
Symbol
fSCL
Parameter
SCL clock frequency
Clock low period
Conditions
Min.
0
Max.
Units
kHz
µs
100
tLOW
tHIGH
tBUF
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
Clock high period
Bus free time (1)
µs
Before new transmission
µs
tSU:STA
tHD:STA
tSU:STO
tAA
Start condition setup time
Start condition hold time
Stop condition setup time
Clock edge to valid output
Data Out hold time (1)
µs
µs
µs
SCL low to valid SDA (cycle n)
3.5
µs
tDH
SCL low (cycle n+1) to SDA change
µs
tR
SCL and SDA rise time (1)
SCL and SDA fall time (1)
Data In setup time (1)
Data In hold time (1)
1000
300
ns
tF
ns
tSU:DAT
tHD:DAT
TI
250
0
ns
ns
Noise filter SCL and SDA (1)
Write cycle time
Noise suppression
100
5
ns
tWR
ms
2033 Table02
Note (1) These values are guaranteed by design.
Table 2. Register Read/Write AC Operating Characteristics
SUMMIT MICROELECTRONICS, Inc.
2033 8.1 10/04/01
10
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
