UPSD3212C, UPSD3212CV
Figure 48. PLD Diagram
8
PAGE
REGISTER
DATA
BUS
DECODE PLD
4
73
PRIMARY FLASH MEMORY SELECTS
2
1
1
2
SECONDARY NON-VOLATILE MEMORY SELECTS
SRAM SELECT
CSIOP SELECT
PERIPHERAL SELECTS
OUTPUT MACROCELL FEEDBACK
CPLD
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
MCELLAB
16
16 OUTPUT
MACROCELL
1
TO PORT A OR B
8
MACROCELL
ALLOC.
PT
ALLOC.
73
MCELLBC
TO PORT B OR C
8
2
20 INPUT MACROCELL
(PORT A,B,C)
EXTERNAL CHIP SELECTS
TO PORT D
DIRECT MACROCELL INPUT TO MCU DATA BUS
INPUT MACROCELL & INPUT PORTS
PORT D INPUTS
20
2
AI07435
Note: 1. Ports A is not available in the 52-pin package
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