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UPSD3412C-24U6T 参数 Datasheet PDF下载

UPSD3412C-24U6T图片预览
型号: UPSD3412C-24U6T
PDF下载: 下载PDF文件 查看货源
内容描述: 闪存可编程系统设备与8032单片机内核和16Kbit的SRAM [Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM]
分类和应用: 闪存静态存储器微控制器
文件页数/大小: 152 页 / 1492 K
品牌: STMICROELECTRONICS [ ST ]
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UPSD3212C, UPSD3212CV  
SFR  
Addressing Modes  
The SFRs can only be addressed directly in the  
address range from 80h to FFh. Table 15, page 32  
gives an overview of the Special Function Regis-  
ters. Sixteen address in the SFRs space are both-  
byte and bit-addressable. The bit-addressable  
SFRs are those whose address ends in 0h and 8h.  
The bit addresses in this area are 80h to FFh.  
The addressing modes in uPSD321X Devices in-  
struction set are as follows  
Direct addressing  
Indirect addressing  
Register addressing  
Register-specific addressing  
Immediate constants addressing  
Indexed addressing  
Table 3. RAM Address  
Byte Address  
(in Hexadecimal)  
Byte Address  
(in Decimal)  
(1) Direct addressing. In a direct addressing the  
operand is specified by an 8-bit address field in the  
instruction. Only internal Data RAM and SFRs  
(80~FFH RAM) can be directly addressed.  
255  
48  
FFh  
30h  
msb  
Example:  
Bit Address (Hex)  
lsb  
mov A, 3EH ;A <----- RAM[3E]  
2Fh 7F 7E 7D 7C 7B 7A 79 78 47  
2Eh 77 76 75 74 73 72 71 70 46  
2Dh 6F 6E 6D 6C 6B 6A 69 68 45  
2Ch 67 66 65 64 63 62 61 60 44  
2Bh 5F 5E 5D 5C 5B 5A 59 58 43  
2Ah 57 56 55 54 53 52 51 50 42  
29h 4F 4E 4D 4C 4B 4A 49 48 41  
28h 47 46 45 44 43 42 41 40 40  
27h 3F 3E 3D 3C 3B 3A 39 38 39  
26h 37 36 35 34 33 32 31 30 38  
25h 2F 2E 2D 2C 2B 2A 29 28 37  
24h 27 26 25 24 23 22 21 20 36  
23h 1F 1E 1D 1C 1B 1A 19 18 35  
22h 17 16 15 14 13 12 11 10 34  
21h 0F 0E 0D 0C 0B 0A 09 08 33  
20h 07 06 05 04 03 02 01 00 32  
Figure 11. Direct Addressing  
Program Memory  
A
3Eh  
04  
AI06641  
(2) Indirect addressing. In indirect addressing  
the instruction specifies a register which contains  
the address of the operand. Both internal and ex-  
ternal RAM can be indirectly addressed. The ad-  
dress register for 8-bit addresses can be R0 or R1  
of the selected register bank, or the Stack Pointer.  
The address register for 16-bit addresses can only  
be the 16-bit “data pointer” register, DPTR.  
Example:  
mov @R1, #40 H ;[R1] <-----40H  
1Fh  
18h  
17h  
10h  
0Fh  
08h  
07h  
00h  
31  
24  
23  
16  
15  
8
Register Bank 3  
Register Bank 2  
Register Bank 1  
Register Bank 0  
Figure 12. Indirect Addressing  
Program Memory  
55h  
R1  
40h  
55  
7
0
AI06642  
20/152  
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