TS5070 - TS5071
TS5070 PIN FUNCTIONALITY (PLCC28)
No.
1
2
3
4
Name
GND
VFR0
VSS
NC
NC
Function
Ground Input(+0V)
Analog Output
Supply Input (-5V)
Not Connected
Not Connected
5
6
7
8
9
IL3
IL2
FSR
DR1
DR0
CO
CI
CCLK
CS
Digital Input or Output defined by LDR register content
Digital Input or Output defined by LDR register content
Digital input
Digital input sampled by BCLK falling edge
Digital input sampled by BCLK falling edge
Digital output (shifted out on CCLK rising edge)
Digital input (sampled on CCLK falling edge)
Digital input (clock)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Digital input (chip select for CI/CO)
Digital Input
Digital input (clock)
MR
BCLK
MCLK
DX0
DX1
TSX0
TSX1
FSX
IL5
IL4
IL1
IL0
VCC
VFXI
Digital input
Digital output clocked by BCLK rising edge
Digital output clocked by BCLK rising edge
Open drain output (pulled low by active DX0 time slot)
Open drain output (pulled low by active DX1 time slot)
Digital input
Digital input or output defined by LDR register content
Digital input or output defined by LDR register content
Digital input or output defined by LDR register content
Digital input or output defined by LDR register content
Supply input (+5V)
Analog input
TS5070 FUNCTIONAL DIAGRAM
VCC=+5V
VSS=-5V
VFXI
ENCODER
AZ
DX0
DX1
TX
TX GAIN
TX TIME SLOT
REGISTER
HYBRID
BALANCE
FILTER
TSX0
TSX1
FSX
Vref
TIME-SLOT
ASSIGNMENT
BCLK
HYBAL 1
CTL REG.
HYBAL 2
HYBAL 3
FSR
VFRO
GND
RX
REGISTER
DR0
DR1
TS5070/71
RX TIME SLOT
MCLK
MR
DECODER
IL5
IL4
RX GAIN
CS
IL3
IL2
LATCH DIR
CCLK
CO
INTERFACE
LATCHES
CONTROL
INTERFACE
LATCH CONT.
IL1
IL0
CI
D94TL135
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STMICROELECTRONICS [ ST ]
