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STM32F405RG 参数 Datasheet PDF下载

STM32F405RG图片预览
型号: STM32F405RG
PDF下载: 下载PDF文件 查看货源
内容描述: ARM的Cortex- M4 32B MCUFPU , 210DMIPS ,高达1MB闪存/ 1924KB RAM , USB OTG HS / FS [ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS]
分类和应用: 闪存
文件页数/大小: 185 页 / 5432 K
品牌: STMICROELECTRONICS [ ST ]
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Description  
STM32F405xx, STM32F407xx  
The device also features an embedded programmable voltage detector (PVD) that monitors  
the V /V  
power supply and compares it to the V  
threshold. An interrupt can be  
DD DDA  
PVD  
generated when V /V  
drops below the V  
threshold and/or when V /V  
is  
DD DDA  
PVD  
DD DDA  
higher than the V  
threshold. The interrupt service routine can then generate a warning  
PVD  
message and/or put the MCU into a safe state. The PVD is enabled by software.  
Internal reset OFF  
This feature is available only on packages featuring the PDR_ON pin. The internal power-on  
reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin.  
An external power supply supervisor should monitor V and should maintain the device in  
DD  
reset mode as long as V is below a specified threshold. PDR_ON should be connected to  
DD  
this external power supply supervisor. Refer to Figure 7: Power supply supervisor  
interconnection with internal reset OFF.  
Figure 7. Power supply supervisor interconnection with internal reset OFF  
VDD  
External VDD power supply supervisor  
Ext. reset controller active when  
VDD < 1.7 V or 1.8 V (1)  
PDR_ON  
Application reset  
signal (optional)  
NRST  
VDD  
MS31383V3  
1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.  
The V specified threshold, below which the device must be maintained under reset, is  
DD  
1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the  
0 to 70 °C temperature range.  
A comprehensive set of power-saving mode allows to design low-power applications.  
When the internal reset is OFF, the following integrated features are no more supported:  
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled  
The brownout reset (BOR) circuitry is disabled  
The embedded programmable voltage detector (PVD) is disabled  
V
functionality is no more available and V  
pin should be connected to V  
BAT DD  
BAT  
All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset  
through the PDR_ON signal.  
24/185  
DocID022152 Rev 4  
 
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