STM32F405xx, STM32F407xx
Description
Figure 6. Multi-AHB matrix
ARM
Cortex-M4
GP
DMA1
GP
DMA2
MAC
Ethernet
64-Kbyte
USB OTG
HS
CCM data RAM
S0
S1
S2
S3
S4
S5
S6
S7
ICODE
M0
Flash
memory
DCODE
M1
SRAM1
M2
M3
M4
M5
112 Kbyte
SRAM2
16 Kbyte
AHB1
APB1
APB2
peripherals
AHB2
peripherals
FSMC
M6
Static MemCtl
Bus matrix-S
ai18490c
2.2.8
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
2
•
•
•
•
•
•
•
•
SPI and I S
2
I C
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDIO
Camera interface (DCMI)
ADC.
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