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STM32F302RC 参数 Datasheet PDF下载

STM32F302RC图片预览
型号: STM32F302RC
PDF下载: 下载PDF文件 查看货源
内容描述: ARM的Cortex- M4F 32B MCUFPU ,高达256 KB的SRAM Flash48KB [ARM Cortex-M4F 32b MCUFPU, up to 256KB Flash48KB SRAM]
分类和应用: 静态存储器
文件页数/大小: 133 页 / 2061 K
品牌: STMICROELECTRONICS [ ST ]
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Electrical characteristics  
STM32F302xx/STM32F303xx  
6.3.17  
Communications interfaces  
I2C interface characteristics  
Unless otherwise specified, the parameters given in Table 59 are derived from tests  
performed under ambient temperature, f  
frequency and V supply voltage conditions  
PCLK1  
DD  
summarized in Table 22.  
2
2
The I C interface meets the requirements of the standard I C communication protocol with  
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-  
drain. When configured as open-drain, the PMOS connected between the I/O pin and V is  
DD  
disabled, but is still present.  
2
The I C characteristics are described in Table 59. Refer also to Section 6.3.14: I/O port  
for more details on the input/output alternate function characteristics (SDA  
characteristics  
and SCL)  
.
2
(1)  
Table 59. I C characteristics  
Standard  
mode  
Fast mode  
Fast Mode Plus  
Symbol  
Parameter  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
tw(SCLL)  
tw(SCLH)  
tsu(SDA)  
th(SDA)  
SCL clock low time  
4.7  
4.0  
-
1.3  
0.6  
-
0.5  
0.26  
50  
-
µs  
SCL clock high time  
SDA setup time  
-
-
-
-
-
250  
0(3)  
-
100  
0(3)  
SDA data hold time  
3450(2)  
900(2)  
0
450  
tr(SDA)  
tr(SCL)  
ns  
SDA and SCL rise time  
SDA and SCL fall time  
-
-
1000  
300  
300  
300  
120  
120  
-
-
-
-
tf(SDA)  
tf(SCL)  
th(STA)  
tsu(STA)  
tsu(STO)  
Start condition hold time  
4.0  
4.7  
4.0  
4.7  
-
-
0.6  
0.6  
0.6  
1.3  
-
-
0.26  
0.26  
0.26  
0.5  
-
-
µs  
Repeated Start condition setup time  
Stop condition setup time  
-
-
-
-
-
-
-
-
-
μs  
μs  
pF  
tw(STO:STA) Stop to Start condition time (bus free)  
Cb Capacitive load for each bus line  
400  
400  
550  
The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when  
I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in  
production.  
1.  
The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal.  
2.  
3.  
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of  
the falling edge of SCL.  
(1)  
Table 60. I2C analog filter characteristics  
Symbol  
Parameter  
Min  
Max  
Unit  
Pulse width of spikes that are  
suppressed by the analog filter  
tSP  
50  
260  
ns  
1. Guaranteed by design, not tested in production.  
96/133  
Doc ID 023353 Rev 5  
 
 
 
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