Electrical characteristics
STM32F302xx/STM32F303xx
SPI/I2S characteristics
2
Unless otherwise specified, the parameters given in Table 61 for SPI or in Table 62 for I S
are derived from tests performed under ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 22.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
2
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).
Table 61. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
-
-
18
18
fSCK
SPI clock frequency
MHz
(1)
1/tc(SCK)
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
-
8
ns
%
(1)
SPI slave input clock
duty cycle
DuCy(SCK)(1)
Slave mode
30
70
(1)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
2Tpclk
4Tpclk
-
-
(1)
th(NSS)
(1)
tw(SCKH)
tw(SCKL)
Master mode, fPCLK = 36 MHz,
presc = 4
Tpclk/2 Tpclk/2
SCK high and low time
Data input setup time
(1)
- 3
5.5
6.5
5
+ 3
(1)
Master mode
Slave mode
Master mode
Slave mode
-
tsu(MI)
tsu(SI)
(1)
-
(1)
th(MI)
-
Data input hold time
ns
(1)
th(SI)
5
-
(1)(2)
ta(SO)
Data output access time Slave mode, fPCLK = 24 MHz
Data output disable time Slave mode
0
4Tpclk
(1)(3)
tdis(SO)
0
24
39
3
(1)
tv(SO)
Data output valid time
Data output valid time
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
(1)
tv(MO)
-
(1)
th(SO)
15
4
-
Data output hold time
(1)
th(MO)
-
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z.
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Doc ID 023353 Rev 5
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