STM32F302xx/STM32F303xx
Electrical characteristics
(1)
Table 57. IWDG min/max timeout period at 40 kHz (LSI)
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
/4
/8
0
1
2
3
4
5
7
0.1
0.2
0.4
0.8
1.6
3.2
6.4
409.6
819.2
/16
/32
/64
/128
/256
1638.4
3276.8
6553.6
13107.2
26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 58. WWDG min-max timeout value @72 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
1
2
4
8
0
1
2
3
0.05687 (1)
0.1137 (1)
0.2275 (1)
0.4551 (1)
3.6409 (1)
7.2817 (1)
14.564 (1)
29.127 (1)
1. Guaranteed by design, not tested in production.
Doc ID 023353 Rev 5
95/133
STMICROELECTRONICS [ ST ]
